MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_KLXX/sleep.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "sleep_api.h"
sahilmgandhi 18:6a4db94011d3 17 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 18 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 //Normal wait mode
sahilmgandhi 18:6a4db94011d3 21 void hal_sleep(void)
sahilmgandhi 18:6a4db94011d3 22 {
sahilmgandhi 18:6a4db94011d3 23 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 //Normal sleep mode for ARM core:
sahilmgandhi 18:6a4db94011d3 26 SCB->SCR = 0;
sahilmgandhi 18:6a4db94011d3 27 __WFI();
sahilmgandhi 18:6a4db94011d3 28 }
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 //Very low-power stop mode
sahilmgandhi 18:6a4db94011d3 31 void hal_deepsleep(void)
sahilmgandhi 18:6a4db94011d3 32 {
sahilmgandhi 18:6a4db94011d3 33 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
sahilmgandhi 18:6a4db94011d3 34 uint8_t ADC_HSC = 0;
sahilmgandhi 18:6a4db94011d3 35 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
sahilmgandhi 18:6a4db94011d3 36 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
sahilmgandhi 18:6a4db94011d3 37 ADC_HSC = 1;
sahilmgandhi 18:6a4db94011d3 38 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
sahilmgandhi 18:6a4db94011d3 39 }
sahilmgandhi 18:6a4db94011d3 40 }
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #if ! defined(TARGET_KL43Z)
sahilmgandhi 18:6a4db94011d3 43 //Check if PLL/FLL is enabled:
sahilmgandhi 18:6a4db94011d3 44 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
sahilmgandhi 18:6a4db94011d3 45 #endif
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
sahilmgandhi 18:6a4db94011d3 48 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 //Deep sleep for ARM core:
sahilmgandhi 18:6a4db94011d3 51 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 __WFI();
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #if ! defined(TARGET_KL43Z)
sahilmgandhi 18:6a4db94011d3 56 //Switch back to PLL as clock source if needed
sahilmgandhi 18:6a4db94011d3 57 //The interrupt that woke up the device will run at reduced speed
sahilmgandhi 18:6a4db94011d3 58 if (PLL_FLL_en) {
sahilmgandhi 18:6a4db94011d3 59 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
sahilmgandhi 18:6a4db94011d3 60 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
sahilmgandhi 18:6a4db94011d3 61 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
sahilmgandhi 18:6a4db94011d3 62 #endif
sahilmgandhi 18:6a4db94011d3 63 MCG->C1 &= ~MCG_C1_CLKS_MASK;
sahilmgandhi 18:6a4db94011d3 64 }
sahilmgandhi 18:6a4db94011d3 65 #endif
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 if (ADC_HSC) {
sahilmgandhi 18:6a4db94011d3 68 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
sahilmgandhi 18:6a4db94011d3 69 }
sahilmgandhi 18:6a4db94011d3 70 }