DCS_TEAM / GSM_PUSHING_BOX_STATE_MACHINE

uses pushing box to publish to google spreadsheets with a state machine instead of a while loop

Fork of GSM_Library by DCS_TEAM

GSMLibrary.cpp@0:41904adca656, 2015-03-05 (annotated)

Committer:
danilob
Date:
Thu Mar 05 20:06:41 2015 +0000
Revision:
0:41904adca656
Child:
2:8352ad91f2ee
new version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
danilob 0:41904adca656 1 #include "GSMLibrary.h"
danilob 0:41904adca656 2 #include "gsmqueue.h"
danilob 0:41904adca656 3
danilob 0:41904adca656 4
danilob 0:41904adca656 5
danilob 0:41904adca656 6 //definition for AT comands
danilob 0:41904adca656 7 #define AT_OK "AT"
danilob 0:41904adca656 8 #define AT_CSQ "AT+CSQ"
danilob 0:41904adca656 9 #define AT_CREG "AT+CREG?"
danilob 0:41904adca656 10 #define AT_CMGF "AT+CMGF=1"
danilob 0:41904adca656 11 #define RECEIVER_PHONE_NUMBER "\"+18014722842\""
danilob 0:41904adca656 12 #define AT_CMGS "AT+CMGS=" RECEIVER_PHONE_NUMBER
danilob 0:41904adca656 13
danilob 0:41904adca656 14 //Definition for at repsonses
danilob 0:41904adca656 15 //Please notice that after ":" the gsm will usually send aditional information
danilob 0:41904adca656 16 #define AT_OK_RESPONSE "OK" //Response after sending "AT" message
danilob 0:41904adca656 17 #define AT_CSQ_RESPONSE "+CSQ:" //+CSQ: <arg1>,<arg2> where <arg1> is signal strenght arg1 = 0-30 where a number below 10 means low signal strength and 99 is not knwn or detectable signal and arg2 is bit error rate form 0-7, 99 will represent error
danilob 0:41904adca656 18 #define AT_CREG_RESPONSE "+CREG:"//+CREG: <arg1>,<arg2> where <arg1> = 0-2(see at comand descriptions), <arg2> = 0-5, 0 not registered to nework and not looking for one. 1 is conected to network, 2 is not conected but searching
danilob 0:41904adca656 19 #define AT_CMGF_RESPONSE "OK"
danilob 0:41904adca656 20 #define AT_CMGS_RESPONSE ">" //Message is written aftersymbol
danilob 0:41904adca656 21 #define AT_SENDSMS_RESPONSE "+CMGS:" // +CMGS: <id> this will include the message id. CMGS ERROR for error and
danilob 0:41904adca656 22 #define AT_SUCCESS_REPSONSE "OK"
danilob 0:41904adca656 23
danilob 0:41904adca656 24
danilob 0:41904adca656 25 extern Serial pc;
danilob 0:41904adca656 26 extern Serial gsm;
danilob 0:41904adca656 27 extern uint8_t buffer[BUFFER_LENGTH];//buffer storing char
danilob 0:41904adca656 28 gsm_states gsm_current_state = GSM_INITIALIZE;
danilob 0:41904adca656 29
danilob 0:41904adca656 30 char correct = 0;
danilob 0:41904adca656 31 char send = 0;
danilob 0:41904adca656 32 char timeout = 0;
danilob 0:41904adca656 33 char received = 0;
danilob 0:41904adca656 34
danilob 0:41904adca656 35 void gsm_tick(){
danilob 0:41904adca656 36 //pre action
danilob 0:41904adca656 37 switch(gsm_current_state){
danilob 0:41904adca656 38 case GSM_INITIALIZE:
danilob 0:41904adca656 39 correct = 0;
danilob 0:41904adca656 40 timeout = 0;
danilob 0:41904adca656 41 received = 0;
danilob 0:41904adca656 42 break;
danilob 0:41904adca656 43 case GSM_AT_OK:
danilob 0:41904adca656 44 break;
danilob 0:41904adca656 45 case GSM_AT_CSQ:
danilob 0:41904adca656 46 break;
danilob 0:41904adca656 47 case GSM_AT_CREG:
danilob 0:41904adca656 48 break;
danilob 0:41904adca656 49 case GSM_AT_CMGF:
danilob 0:41904adca656 50 break;
danilob 0:41904adca656 51 case GSM_AT_CMGS:
danilob 0:41904adca656 52 break;
danilob 0:41904adca656 53 case GSM_AT_SENDSMS:
danilob 0:41904adca656 54 break;
danilob 0:41904adca656 55 case GSM_SUCCESS:
danilob 0:41904adca656 56 break;
danilob 0:41904adca656 57 }
danilob 0:41904adca656 58
danilob 0:41904adca656 59 //post action
danilob 0:41904adca656 60 switch(gsm_current_state){
danilob 0:41904adca656 61 case GSM_INITIALIZE:
danilob 0:41904adca656 62 if(send){
danilob 0:41904adca656 63 gsm.puts(AT_OK);
danilob 0:41904adca656 64 gsm.puts("\r\n");
danilob 0:41904adca656 65 gsm_current_state = GSM_AT_OK;
danilob 0:41904adca656 66 }
danilob 0:41904adca656 67 else
danilob 0:41904adca656 68 gsm_current_state = GSM_INITIALIZE;
danilob 0:41904adca656 69 break;
danilob 0:41904adca656 70 case GSM_AT_OK:
danilob 0:41904adca656 71
danilob 0:41904adca656 72 gsm_current_state = GSM_AT_CSQ;
danilob 0:41904adca656 73 break;
danilob 0:41904adca656 74 case GSM_AT_CSQ:
danilob 0:41904adca656 75 gsm_current_state = GSM_AT_CREG;
danilob 0:41904adca656 76 break;
danilob 0:41904adca656 77 case GSM_AT_CREG:
danilob 0:41904adca656 78 gsm_current_state = GSM_AT_CMGF;
danilob 0:41904adca656 79 break;
danilob 0:41904adca656 80 case GSM_AT_CMGF:
danilob 0:41904adca656 81 gsm_current_state = GSM_AT_CMGS;
danilob 0:41904adca656 82 break;
danilob 0:41904adca656 83 case GSM_AT_CMGS:
danilob 0:41904adca656 84 gsm_current_state = GSM_AT_SENDSMS;
danilob 0:41904adca656 85 break;
danilob 0:41904adca656 86 case GSM_AT_SENDSMS:
danilob 0:41904adca656 87 gsm_current_state = GSM_SUCCESS;
danilob 0:41904adca656 88 break;
danilob 0:41904adca656 89 case GSM_SUCCESS:
danilob 0:41904adca656 90 gsm_current_state = GSM_INITIALIZE;
danilob 0:41904adca656 91 break;
danilob 0:41904adca656 92 default:
danilob 0:41904adca656 93 pc.printf("This is a state error");
danilob 0:41904adca656 94 }
danilob 0:41904adca656 95
danilob 0:41904adca656 96 }
danilob 0:41904adca656 97
danilob 0:41904adca656 98 //
danilob 0:41904adca656 99 void gsm_reset();
danilob 0:41904adca656 100
danilob 0:41904adca656 101
danilob 0:41904adca656 102 //
danilob 0:41904adca656 103 void gsm_initialize(){
danilob 0:41904adca656 104 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
danilob 0:41904adca656 105 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
danilob 0:41904adca656 106 pc.printf("initializing tregisters...!\r\n");
danilob 0:41904adca656 107 // control register mux, enabling uart3 receive
danilob 0:41904adca656 108 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(8);
danilob 0:41904adca656 109
danilob 0:41904adca656 110 // Enable request signal for channel 0
danilob 0:41904adca656 111 DMA_ERQ = DMA_ERQ_ERQ0_MASK;
danilob 0:41904adca656 112
danilob 0:41904adca656 113 // select round-robin arbitration priority
danilob 0:41904adca656 114 DMA_CR |= DMA_CR_ERCA_MASK;
danilob 0:41904adca656 115
danilob 0:41904adca656 116 //enabled error interrupt for DMA0
danilob 0:41904adca656 117 //DMA_EEI = DMA_EEI_EEI0_MASK ;
danilob 0:41904adca656 118 //Addres for buffer
danilob 0:41904adca656 119 DMA_TCD0_SADDR = (uint32_t) &UART_D_REG(UART3_BASE_PTR);
danilob 0:41904adca656 120 DMA_TCD0_DADDR = (uint32_t) buffer;
danilob 0:41904adca656 121 // Set an offset for source and destination address
danilob 0:41904adca656 122 DMA_TCD0_SOFF = 0x00;
danilob 0:41904adca656 123 DMA_TCD0_DOFF = 0x01; // Destination address offset of 1 byte per transaction
danilob 0:41904adca656 124
danilob 0:41904adca656 125 // Set source and destination data transfer size
danilob 0:41904adca656 126 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0);
danilob 0:41904adca656 127
danilob 0:41904adca656 128 // Number of bytes to be transfered in each service request of the channel
danilob 0:41904adca656 129 DMA_TCD0_NBYTES_MLNO = 0x01;
danilob 0:41904adca656 130 // Current major iteration count
danilob 0:41904adca656 131 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(BUFFER_LENGTH);
danilob 0:41904adca656 132 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(BUFFER_LENGTH);
danilob 0:41904adca656 133 // Adjustment value used to restore the source and destiny address to the initial value
danilob 0:41904adca656 134 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
danilob 0:41904adca656 135 DMA_TCD0_SLAST = 0; // Source address adjustment
danilob 0:41904adca656 136 DMA_TCD0_DLASTSGA = -BUFFER_LENGTH; // Destination address adjustment
danilob 0:41904adca656 137 // Setup control and status register
danilob 0:41904adca656 138 DMA_TCD0_CSR = 0;
danilob 0:41904adca656 139
danilob 0:41904adca656 140 // enable interrupt call at end of major loop
danilob 0:41904adca656 141 DMA_TCD0_CSR |= DMA_CSR_INTMAJOR_MASK;
danilob 0:41904adca656 142
danilob 0:41904adca656 143 //Activate dma trasnfer rx interrupt
danilob 0:41904adca656 144 UART_C2_REG(UART3) |= UART_C2_RIE_MASK;
danilob 0:41904adca656 145 UART_C5_REG(UART3) |= UART_C5_RDMAS_MASK | UART_C5_ILDMAS_MASK | UART_C5_LBKDDMAS_MASK;
danilob 0:41904adca656 146 //activate p fifo
danilob 0:41904adca656 147 UART_PFIFO_REG(UART3) |= UART_PFIFO_RXFE_MASK; //RXFE and buffer size of 1 word
danilob 0:41904adca656 148 pc.printf("Initialization done...\n\r");
danilob 0:41904adca656 149 }
danilob 0:41904adca656 150
danilob 0:41904adca656 151
danilob 0:41904adca656 152
danilob 0:41904adca656 153 //initialization debuging purposes
danilob 0:41904adca656 154 void print_registers() {
danilob 0:41904adca656 155
danilob 0:41904adca656 156
danilob 0:41904adca656 157 pc.printf("\n\rDMA REGISTERS\n\r");
danilob 0:41904adca656 158 pc.printf("DMA_MUX: 0x%08x\r\n",DMAMUX_CHCFG0);
danilob 0:41904adca656 159 pc.printf("SADDR0: 0x%08x\r\n",DMA_TCD0_SADDR);
danilob 0:41904adca656 160 pc.printf("DADDR0: 0x%08x\r\n",DMA_TCD0_DADDR);
danilob 0:41904adca656 161 pc.printf("CITER0: 0x%08x\r\n",DMA_TCD0_CITER_ELINKNO);
danilob 0:41904adca656 162 pc.printf("BITER0: 0x%08x\r\n",DMA_TCD0_BITER_ELINKNO);
danilob 0:41904adca656 163 pc.printf("DMA_CR: %08x\r\n", DMA_CR);
danilob 0:41904adca656 164 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
danilob 0:41904adca656 165 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
danilob 0:41904adca656 166 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
danilob 0:41904adca656 167 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
danilob 0:41904adca656 168 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
danilob 0:41904adca656 169 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
danilob 0:41904adca656 170 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
danilob 0:41904adca656 171 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
danilob 0:41904adca656 172 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
danilob 0:41904adca656 173 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
danilob 0:41904adca656 174 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
danilob 0:41904adca656 175 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
danilob 0:41904adca656 176 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
danilob 0:41904adca656 177 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);
danilob 0:41904adca656 178 pc.printf("DMA_TCD0_DOFF: %08x\r\n",DMA_TCD0_DOFF);
danilob 0:41904adca656 179 pc.printf("\n\rUART REGISTERS\n\r");
danilob 0:41904adca656 180 pc.printf("UART_BDH_REG: %08x\r\n",UART_BDH_REG(UART3));
danilob 0:41904adca656 181 pc.printf("UART_C1_REG: %08x\r\n",UART_C1_REG(UART3));
danilob 0:41904adca656 182 pc.printf("UART_C2_REG: %08x\r\n",UART_C2_REG(UART3));
danilob 0:41904adca656 183 pc.printf("UART_S1_REG: %08x\r\n",UART_S1_REG(UART3));
danilob 0:41904adca656 184 pc.printf("UART_s2_REG: %08x\r\n",UART_S2_REG(UART3));
danilob 0:41904adca656 185 pc.printf("UART_C3_REG: %08x\r\n",UART_C3_REG(UART3));
danilob 0:41904adca656 186 pc.printf("UART_D_REG: %08x\r\n",UART_D_REG(UART3));
danilob 0:41904adca656 187 pc.printf("UART_MA1_REG: %08x\r\n",UART_MA1_REG(UART3));
danilob 0:41904adca656 188 pc.printf("UART_MA2_REG: %08x\r\n",UART_MA2_REG(UART3));
danilob 0:41904adca656 189 pc.printf("UART_C4_REG: %08x\r\n",UART_C4_REG(UART3));
danilob 0:41904adca656 190 pc.printf("UART_C5_REG: %08x\r\n",UART_C5_REG(UART3));
danilob 0:41904adca656 191 pc.printf("UART_ED_REG: %08x\r\n",UART_ED_REG(UART3));
danilob 0:41904adca656 192 pc.printf("UART_MODEM_REG: %08x\r\n",UART_MODEM_REG(UART3));
danilob 0:41904adca656 193 pc.printf("UART_IR_REG: %08x\r\n",UART_IR_REG(UART3));
danilob 0:41904adca656 194 pc.printf("UART_PFIFO_REG: %08x\r\n",UART_PFIFO_REG(UART3));
danilob 0:41904adca656 195 pc.printf("UART_CFIFO_REG: %08x\r\n",UART_CFIFO_REG(UART3));
danilob 0:41904adca656 196 pc.printf("UART_SFIFO_REG: %08x\r\n",UART_SFIFO_REG(UART3));
danilob 0:41904adca656 197 pc.printf("UART_TWFIFO_REG: %08x\r\n",UART_TWFIFO_REG(UART3));
danilob 0:41904adca656 198 pc.printf("UART_TCFIFO_REG: %08x\r\n",UART_TCFIFO_REG(UART3));
danilob 0:41904adca656 199 pc.printf("UART_RWFIFO_REG: %08x\r\n",UART_RWFIFO_REG(UART3));
danilob 0:41904adca656 200 pc.printf("UART_RCFIFO_REG: %08x\r\n",UART_RCFIFO_REG(UART3));
danilob 0:41904adca656 201
danilob 0:41904adca656 202 }