DCS_TEAM / GSM_PUSHING_BOX_STATE_MACHINE

uses pushing box to publish to google spreadsheets with a state machine instead of a while loop

Fork of GSM_Library by DCS_TEAM

GSMLibrary.cpp@15:19ae032e2e54, 2015-03-06 (annotated)

Committer:
danilob
Date:
Fri Mar 06 02:45:22 2015 +0000
Revision:
15:19ae032e2e54
Parent:
14:56a2c371ce18
Child:
16:6807d437cd48
gsm working

Who changed what in which revision?

UserRevisionLine numberNew contents of line
danilob 0:41904adca656 1 #include "GSMLibrary.h"
danilob 0:41904adca656 2 #include "gsmqueue.h"
danilob 2:8352ad91f2ee 3 #include <string.h>
danilob 0:41904adca656 4
danilob 15:19ae032e2e54 5 #define TIME_CONST .3
danilob 15:19ae032e2e54 6 #define SECONDS_TIMEOUT 40
danilob 15:19ae032e2e54 7 #define TIMEOUTLIMIT SECONDS_TIMEOUT/TIME_CONST //$change check with main code this will set up condition fior timeout.
danilob 0:41904adca656 8
danilob 0:41904adca656 9 //definition for AT comands
danilob 0:41904adca656 10 #define AT_OK "AT"
danilob 0:41904adca656 11 #define AT_CSQ "AT+CSQ"
danilob 0:41904adca656 12 #define AT_CREG "AT+CREG?"
danilob 0:41904adca656 13 #define AT_CMGF "AT+CMGF=1"
danilob 0:41904adca656 14 #define RECEIVER_PHONE_NUMBER "\"+18014722842\""
danilob 0:41904adca656 15 #define AT_CMGS "AT+CMGS=" RECEIVER_PHONE_NUMBER
danilob 15:19ae032e2e54 16 #define MESSAGE_BODY "stress test\32\32"
danilob 0:41904adca656 17
danilob 0:41904adca656 18 //Definition for at repsonses
danilob 0:41904adca656 19 //Please notice that after ":" the gsm will usually send aditional information
danilob 0:41904adca656 20 #define AT_OK_RESPONSE "OK" //Response after sending "AT" message
es_marble 6:3ccc86304c2c 21 #define AT_CSQ_RESPONSE "+CSQ:" //+CSQ: <arg1>,<arg2> where <arg1> is signal strength arg1 = 0-30 where a number below 10 means low signal strength and 99 is not knwn or detectable signal and arg2 is bit error rate form 0-7, 99 will represent error
danilob 13:9ac5ff131214 22 #define AT_CREG_RESPONSE "+CREG:"//+CREG: <arg1>,<arg2> where <arg1> = 0-2(see AT command descriptions), <arg2> = 0-5, 0 not registered to nework and not looking for one. 1 is conected to network, 2 is not conected but searching
danilob 0:41904adca656 23 #define AT_CMGF_RESPONSE "OK"
danilob 14:56a2c371ce18 24 #define AT_CMGS_RESPONSE ">" //Message is written aftersymbol
danilob 15:19ae032e2e54 25 #define AT_SENDSMS_RESPONSE ">" // +CMGS: <id> this will include the message id. CMGS ERROR for error and
danilob 15:19ae032e2e54 26 #define AT_SUCCESS_REPSONSE "+CMGS:"
danilob 0:41904adca656 27
danilob 0:41904adca656 28
danilob 0:41904adca656 29 extern Serial pc;
danilob 0:41904adca656 30 extern Serial gsm;
danilob 0:41904adca656 31 extern uint8_t buffer[BUFFER_LENGTH];//buffer storing char
danilob 0:41904adca656 32 gsm_states gsm_current_state = GSM_INITIALIZE;
danilob 0:41904adca656 33
danilob 0:41904adca656 34 char send = 0;
danilob 12:f3ccc43c4d3c 35 int timeout_count = 0;
danilob 2:8352ad91f2ee 36 char timeout_limit = TIMEOUTLIMIT;
danilob 0:41904adca656 37
danilob 0:41904adca656 38 void gsm_tick(){
danilob 15:19ae032e2e54 39 if(++timeout_count >= timeout_limit){
danilob 15:19ae032e2e54 40 timeout_count=0;
danilob 15:19ae032e2e54 41 gsm_current_state = GSM_INITIALIZE;
danilob 15:19ae032e2e54 42 }
danilob 0:41904adca656 43 switch(gsm_current_state){
danilob 2:8352ad91f2ee 44 //when send flag is on , send AT_OK message to gsm.
danilob 0:41904adca656 45 case GSM_INITIALIZE:
danilob 2:8352ad91f2ee 46 pc.printf("gsm_initilize state\r\n");//&debug
danilob 2:8352ad91f2ee 47 timeout_count = 0;
danilob 2:8352ad91f2ee 48 if(send){ //send first at_ok message
danilob 2:8352ad91f2ee 49 resetGSMIdleBit();
danilob 2:8352ad91f2ee 50 pc.printf("sending AT_OK\r\n");//&debug
danilob 0:41904adca656 51 gsm.puts(AT_OK);
danilob 12:f3ccc43c4d3c 52 gsm.puts("\r\n");
danilob 2:8352ad91f2ee 53 gsm_current_state = GSM_AT_OK;
danilob 0:41904adca656 54 }
danilob 0:41904adca656 55 else
danilob 0:41904adca656 56 gsm_current_state = GSM_INITIALIZE;
danilob 0:41904adca656 57 break;
danilob 12:f3ccc43c4d3c 58
danilob 2:8352ad91f2ee 59 // check for repsonse to AT and if correct send AT+CSQ message
danilob 0:41904adca656 60 case GSM_AT_OK:
danilob 12:f3ccc43c4d3c 61 pc.printf("inside AT_OK state\r\n");//&debug
danilob 2:8352ad91f2ee 62 if(getGSMIdleBit()){
danilob 2:8352ad91f2ee 63 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 64 if(findInQueue(AT_OK_RESPONSE)){
danilob 2:8352ad91f2ee 65 resetGSMIdleBit();
danilob 2:8352ad91f2ee 66 pc.printf("sending AT_CSQ\r\n");//&debug
danilob 2:8352ad91f2ee 67 gsm.puts(AT_CSQ);
danilob 2:8352ad91f2ee 68 gsm.puts("\r\n");
danilob 2:8352ad91f2ee 69 gsm_current_state = GSM_AT_CSQ;
danilob 2:8352ad91f2ee 70 }
danilob 12:f3ccc43c4d3c 71 else{
danilob 15:19ae032e2e54 72 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 73 gsm.puts(AT_OK);
danilob 12:f3ccc43c4d3c 74 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 75 }
danilob 2:8352ad91f2ee 76 }
danilob 12:f3ccc43c4d3c 77 break;
danilob 12:f3ccc43c4d3c 78
danilob 12:f3ccc43c4d3c 79 //CHECK FOR RESPOSE TO at+csq AND SEND at+creg
danilob 12:f3ccc43c4d3c 80 case GSM_AT_CSQ:
danilob 12:f3ccc43c4d3c 81 pc.printf("inside AT_CSQ state \r\n");//&debug
danilob 12:f3ccc43c4d3c 82 if(getGSMIdleBit()){
danilob 12:f3ccc43c4d3c 83 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 84 if(findInQueue(AT_CSQ_RESPONSE)){
danilob 12:f3ccc43c4d3c 85 if(parseInt() > 9){
danilob 12:f3ccc43c4d3c 86 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 87 pc.printf("sending AT_CREG\r\n");//&debug
danilob 12:f3ccc43c4d3c 88 gsm.puts(AT_CREG);
danilob 12:f3ccc43c4d3c 89 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 90 gsm_current_state = GSM_AT_CREG;
danilob 12:f3ccc43c4d3c 91 }
danilob 12:f3ccc43c4d3c 92 }
danilob 12:f3ccc43c4d3c 93 else{
danilob 15:19ae032e2e54 94 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 95 gsm.puts(AT_CSQ);
danilob 12:f3ccc43c4d3c 96 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 97 }
danilob 12:f3ccc43c4d3c 98 }
danilob 2:8352ad91f2ee 99 break;
danilob 0:41904adca656 100
danilob 12:f3ccc43c4d3c 101 //check for AT creg and if correct send AT+CMGF
danilob 0:41904adca656 102 case GSM_AT_CREG:
danilob 7:6c0b6ab3cafe 103 pc.printf("gsm_creg state\r\n");//&debug
danilob 12:f3ccc43c4d3c 104 if(getGSMIdleBit()){
danilob 12:f3ccc43c4d3c 105 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 106 if(findInQueue(AT_CREG_RESPONSE)){
danilob 13:9ac5ff131214 107 pc.printf("creg parse Int1: %d\r\n",parseInt());//&debug
danilob 13:9ac5ff131214 108 int q = parseInt();
danilob 13:9ac5ff131214 109 pc.printf("creg parse Int2: %d\r\n",q);//&debug
danilob 13:9ac5ff131214 110 if(q == 1){
danilob 12:f3ccc43c4d3c 111 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 112 pc.printf("sending AT_CMGF\r\n");//&debug
danilob 12:f3ccc43c4d3c 113 gsm.puts(AT_CMGF);
danilob 12:f3ccc43c4d3c 114 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 115 gsm_current_state = GSM_AT_CMGF;
danilob 12:f3ccc43c4d3c 116 }
danilob 12:f3ccc43c4d3c 117 }
danilob 12:f3ccc43c4d3c 118 if(gsm_current_state == GSM_AT_CREG){
danilob 15:19ae032e2e54 119 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 120 gsm.puts(AT_CREG);
danilob 12:f3ccc43c4d3c 121 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 122 }
danilob 12:f3ccc43c4d3c 123 }
danilob 0:41904adca656 124 break;
danilob 12:f3ccc43c4d3c 125
danilob 12:f3ccc43c4d3c 126 //check for cmgf esponse and if correct go to at_cmgs
danilob 0:41904adca656 127 case GSM_AT_CMGF:
danilob 12:f3ccc43c4d3c 128 pc.printf("gsm_cmgf state\r\n");//&debug
danilob 12:f3ccc43c4d3c 129 if(getGSMIdleBit()){
danilob 12:f3ccc43c4d3c 130 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 131 if(findInQueue(AT_CMGF_RESPONSE)){
danilob 12:f3ccc43c4d3c 132 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 133 pc.printf("sending AT_CMGS\r\n");//&debug
danilob 12:f3ccc43c4d3c 134 gsm.puts(AT_CMGS);
danilob 12:f3ccc43c4d3c 135 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 136 gsm_current_state = GSM_AT_CMGS;
danilob 12:f3ccc43c4d3c 137 }
danilob 12:f3ccc43c4d3c 138 else{
danilob 15:19ae032e2e54 139 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 140 gsm.puts(AT_CMGF);
danilob 12:f3ccc43c4d3c 141 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 142 }
danilob 12:f3ccc43c4d3c 143 }
danilob 0:41904adca656 144 break;
danilob 12:f3ccc43c4d3c 145
danilob 12:f3ccc43c4d3c 146 //check cmgs response if correct send SMS
danilob 0:41904adca656 147 case GSM_AT_CMGS:
danilob 7:6c0b6ab3cafe 148 pc.printf("gsm_cmgs state\r\n");//&debug
danilob 12:f3ccc43c4d3c 149 if(getGSMIdleBit()){
danilob 12:f3ccc43c4d3c 150 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 151 if(findInQueue(AT_CMGS_RESPONSE)){
danilob 12:f3ccc43c4d3c 152 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 153 pc.printf("sending MESSAGE_BODY\r\n");//&debug
danilob 12:f3ccc43c4d3c 154 gsm.puts(MESSAGE_BODY); //substitute
danilob 12:f3ccc43c4d3c 155 gsm.puts("\r\n");
danilob 15:19ae032e2e54 156 flushQueue();
danilob 12:f3ccc43c4d3c 157 gsm_current_state = GSM_AT_SENDSMS;
danilob 12:f3ccc43c4d3c 158 }
danilob 12:f3ccc43c4d3c 159 else
danilob 12:f3ccc43c4d3c 160 {
danilob 15:19ae032e2e54 161 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 162 gsm.puts(AT_CMGS);
danilob 12:f3ccc43c4d3c 163 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 164 }
danilob 12:f3ccc43c4d3c 165 }
danilob 0:41904adca656 166 break;
danilob 12:f3ccc43c4d3c 167
danilob 12:f3ccc43c4d3c 168 //check if message was sent correctly and if so
danilob 0:41904adca656 169 case GSM_AT_SENDSMS:
danilob 12:f3ccc43c4d3c 170 pc.printf("gsm_send_sms state\r\n");//&debug
danilob 12:f3ccc43c4d3c 171 if(getGSMIdleBit()){
danilob 12:f3ccc43c4d3c 172 printQueue(); //$debug
danilob 15:19ae032e2e54 173
danilob 15:19ae032e2e54 174 if(findInQueue(AT_SENDSMS_RESPONSE)){
danilob 12:f3ccc43c4d3c 175 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 176 gsm_current_state = GSM_SUCCESS;
danilob 12:f3ccc43c4d3c 177 }
danilob 12:f3ccc43c4d3c 178 else
danilob 12:f3ccc43c4d3c 179 {
danilob 15:19ae032e2e54 180 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 181 gsm.puts(AT_CMGF);
danilob 12:f3ccc43c4d3c 182 gsm.puts("\r\n");
danilob 15:19ae032e2e54 183 gsm_current_state = GSM_AT_CMGS;
danilob 12:f3ccc43c4d3c 184 }
danilob 12:f3ccc43c4d3c 185 }
danilob 0:41904adca656 186 break;
danilob 12:f3ccc43c4d3c 187
danilob 12:f3ccc43c4d3c 188
danilob 0:41904adca656 189 case GSM_SUCCESS:
danilob 7:6c0b6ab3cafe 190 pc.printf("gsm_success state\r\n");//&debug
danilob 15:19ae032e2e54 191 if(findInQueue(AT_SENDSMS_RESPONSE)){
danilob 15:19ae032e2e54 192 pc.printf("sending message ID: %iY\r\n",parseInt());//&debug
danilob 12:f3ccc43c4d3c 193 pc.printf("Message SENT!\r\n");//&debug
danilob 15:19ae032e2e54 194 }
danilob 15:19ae032e2e54 195 resetGSMIdleBit();
danilob 15:19ae032e2e54 196 gsm.puts(AT_CMGS);
danilob 15:19ae032e2e54 197 gsm.puts("\r\n");
danilob 15:19ae032e2e54 198 gsm_current_state = GSM_AT_CMGS;
danilob 0:41904adca656 199 break;
danilob 0:41904adca656 200 default:
danilob 0:41904adca656 201 pc.printf("This is a state error");
danilob 0:41904adca656 202 }
danilob 0:41904adca656 203
danilob 0:41904adca656 204 }
danilob 7:6c0b6ab3cafe 205 //set send falg on
danilob 7:6c0b6ab3cafe 206 void gsm_send_sms(){
danilob 7:6c0b6ab3cafe 207 send = 1;
danilob 7:6c0b6ab3cafe 208 }
danilob 0:41904adca656 209 //
danilob 0:41904adca656 210 void gsm_reset();
danilob 0:41904adca656 211
danilob 0:41904adca656 212
danilob 0:41904adca656 213 //
danilob 0:41904adca656 214 void gsm_initialize(){
danilob 7:6c0b6ab3cafe 215 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK; //enabling dmamux clock
danilob 12:f3ccc43c4d3c 216 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK; // enebaling dma clock
danilob 0:41904adca656 217 pc.printf("initializing tregisters...!\r\n");
danilob 0:41904adca656 218 // control register mux, enabling uart3 receive
danilob 0:41904adca656 219 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(8);
danilob 0:41904adca656 220
danilob 0:41904adca656 221 // Enable request signal for channel 0
danilob 0:41904adca656 222 DMA_ERQ = DMA_ERQ_ERQ0_MASK;
danilob 0:41904adca656 223
danilob 0:41904adca656 224 // select round-robin arbitration priority
danilob 0:41904adca656 225 DMA_CR |= DMA_CR_ERCA_MASK;
danilob 0:41904adca656 226
danilob 0:41904adca656 227 //enabled error interrupt for DMA0
danilob 0:41904adca656 228 //DMA_EEI = DMA_EEI_EEI0_MASK ;
danilob 0:41904adca656 229 //Addres for buffer
danilob 0:41904adca656 230 DMA_TCD0_SADDR = (uint32_t) &UART_D_REG(UART3_BASE_PTR);
danilob 0:41904adca656 231 DMA_TCD0_DADDR = (uint32_t) buffer;
danilob 0:41904adca656 232 // Set an offset for source and destination address
danilob 0:41904adca656 233 DMA_TCD0_SOFF = 0x00;
danilob 0:41904adca656 234 DMA_TCD0_DOFF = 0x01; // Destination address offset of 1 byte per transaction
danilob 0:41904adca656 235
danilob 0:41904adca656 236 // Set source and destination data transfer size
danilob 0:41904adca656 237 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0);
danilob 0:41904adca656 238
danilob 0:41904adca656 239 // Number of bytes to be transfered in each service request of the channel
danilob 0:41904adca656 240 DMA_TCD0_NBYTES_MLNO = 0x01;
danilob 0:41904adca656 241 // Current major iteration count
danilob 0:41904adca656 242 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(BUFFER_LENGTH);
danilob 0:41904adca656 243 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(BUFFER_LENGTH);
danilob 0:41904adca656 244 // Adjustment value used to restore the source and destiny address to the initial value
danilob 0:41904adca656 245 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
danilob 0:41904adca656 246 DMA_TCD0_SLAST = 0; // Source address adjustment
danilob 0:41904adca656 247 DMA_TCD0_DLASTSGA = -BUFFER_LENGTH; // Destination address adjustment
danilob 0:41904adca656 248 // Setup control and status register
danilob 0:41904adca656 249 DMA_TCD0_CSR = 0;
danilob 0:41904adca656 250
danilob 0:41904adca656 251 // enable interrupt call at end of major loop
danilob 0:41904adca656 252 DMA_TCD0_CSR |= DMA_CSR_INTMAJOR_MASK;
danilob 0:41904adca656 253
danilob 0:41904adca656 254 //Activate dma trasnfer rx interrupt
danilob 0:41904adca656 255 UART_C2_REG(UART3) |= UART_C2_RIE_MASK;
danilob 0:41904adca656 256 UART_C5_REG(UART3) |= UART_C5_RDMAS_MASK | UART_C5_ILDMAS_MASK | UART_C5_LBKDDMAS_MASK;
danilob 0:41904adca656 257 //activate p fifo
danilob 0:41904adca656 258 UART_PFIFO_REG(UART3) |= UART_PFIFO_RXFE_MASK; //RXFE and buffer size of 1 word
danilob 7:6c0b6ab3cafe 259 queueInit();
danilob 0:41904adca656 260 pc.printf("Initialization done...\n\r");
danilob 0:41904adca656 261 }
danilob 0:41904adca656 262
danilob 0:41904adca656 263
danilob 0:41904adca656 264
danilob 0:41904adca656 265 //initialization debuging purposes
danilob 0:41904adca656 266 void print_registers() {
danilob 0:41904adca656 267
danilob 0:41904adca656 268
danilob 0:41904adca656 269 pc.printf("\n\rDMA REGISTERS\n\r");
danilob 0:41904adca656 270 pc.printf("DMA_MUX: 0x%08x\r\n",DMAMUX_CHCFG0);
danilob 0:41904adca656 271 pc.printf("SADDR0: 0x%08x\r\n",DMA_TCD0_SADDR);
danilob 0:41904adca656 272 pc.printf("DADDR0: 0x%08x\r\n",DMA_TCD0_DADDR);
danilob 0:41904adca656 273 pc.printf("CITER0: 0x%08x\r\n",DMA_TCD0_CITER_ELINKNO);
danilob 0:41904adca656 274 pc.printf("BITER0: 0x%08x\r\n",DMA_TCD0_BITER_ELINKNO);
danilob 0:41904adca656 275 pc.printf("DMA_CR: %08x\r\n", DMA_CR);
danilob 0:41904adca656 276 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
danilob 0:41904adca656 277 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
danilob 0:41904adca656 278 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
danilob 0:41904adca656 279 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
danilob 0:41904adca656 280 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
danilob 0:41904adca656 281 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
danilob 0:41904adca656 282 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
danilob 0:41904adca656 283 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
danilob 0:41904adca656 284 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
danilob 0:41904adca656 285 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
danilob 0:41904adca656 286 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
danilob 0:41904adca656 287 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
danilob 0:41904adca656 288 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
danilob 0:41904adca656 289 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);
danilob 0:41904adca656 290 pc.printf("DMA_TCD0_DOFF: %08x\r\n",DMA_TCD0_DOFF);
danilob 0:41904adca656 291 pc.printf("\n\rUART REGISTERS\n\r");
danilob 0:41904adca656 292 pc.printf("UART_BDH_REG: %08x\r\n",UART_BDH_REG(UART3));
danilob 0:41904adca656 293 pc.printf("UART_C1_REG: %08x\r\n",UART_C1_REG(UART3));
danilob 0:41904adca656 294 pc.printf("UART_C2_REG: %08x\r\n",UART_C2_REG(UART3));
danilob 0:41904adca656 295 pc.printf("UART_S1_REG: %08x\r\n",UART_S1_REG(UART3));
danilob 0:41904adca656 296 pc.printf("UART_s2_REG: %08x\r\n",UART_S2_REG(UART3));
danilob 0:41904adca656 297 pc.printf("UART_C3_REG: %08x\r\n",UART_C3_REG(UART3));
danilob 0:41904adca656 298 pc.printf("UART_D_REG: %08x\r\n",UART_D_REG(UART3));
danilob 0:41904adca656 299 pc.printf("UART_MA1_REG: %08x\r\n",UART_MA1_REG(UART3));
danilob 0:41904adca656 300 pc.printf("UART_MA2_REG: %08x\r\n",UART_MA2_REG(UART3));
danilob 0:41904adca656 301 pc.printf("UART_C4_REG: %08x\r\n",UART_C4_REG(UART3));
danilob 0:41904adca656 302 pc.printf("UART_C5_REG: %08x\r\n",UART_C5_REG(UART3));
danilob 0:41904adca656 303 pc.printf("UART_ED_REG: %08x\r\n",UART_ED_REG(UART3));
danilob 0:41904adca656 304 pc.printf("UART_MODEM_REG: %08x\r\n",UART_MODEM_REG(UART3));
danilob 0:41904adca656 305 pc.printf("UART_IR_REG: %08x\r\n",UART_IR_REG(UART3));
danilob 0:41904adca656 306 pc.printf("UART_PFIFO_REG: %08x\r\n",UART_PFIFO_REG(UART3));
danilob 0:41904adca656 307 pc.printf("UART_CFIFO_REG: %08x\r\n",UART_CFIFO_REG(UART3));
danilob 0:41904adca656 308 pc.printf("UART_SFIFO_REG: %08x\r\n",UART_SFIFO_REG(UART3));
danilob 0:41904adca656 309 pc.printf("UART_TWFIFO_REG: %08x\r\n",UART_TWFIFO_REG(UART3));
danilob 0:41904adca656 310 pc.printf("UART_TCFIFO_REG: %08x\r\n",UART_TCFIFO_REG(UART3));
danilob 0:41904adca656 311 pc.printf("UART_RWFIFO_REG: %08x\r\n",UART_RWFIFO_REG(UART3));
danilob 0:41904adca656 312 pc.printf("UART_RCFIFO_REG: %08x\r\n",UART_RCFIFO_REG(UART3));
danilob 0:41904adca656 313
danilob 0:41904adca656 314 }