strat des robots
Fork of CRAC-Strat_2017 by
mbed/LPC1768/core_cmFunc.h@17:d1594579eec6, 2017-05-19 (annotated)
- Committer:
- ClementBreteau
- Date:
- Fri May 19 17:14:07 2017 +0000
- Revision:
- 17:d1594579eec6
- Parent:
- 0:ad97421fb1fb
strat du robot, 19-05-2017, 19h
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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antbig | 0:ad97421fb1fb | 1 | /**************************************************************************//** |
antbig | 0:ad97421fb1fb | 2 | * @file core_cmFunc.h |
antbig | 0:ad97421fb1fb | 3 | * @brief CMSIS Cortex-M Core Function Access Header File |
antbig | 0:ad97421fb1fb | 4 | * @version V3.00 |
antbig | 0:ad97421fb1fb | 5 | * @date 09. December 2011 |
antbig | 0:ad97421fb1fb | 6 | * |
antbig | 0:ad97421fb1fb | 7 | * @note |
antbig | 0:ad97421fb1fb | 8 | * Copyright (C) 2009-2011 ARM Limited. All rights reserved. |
antbig | 0:ad97421fb1fb | 9 | * |
antbig | 0:ad97421fb1fb | 10 | * @par |
antbig | 0:ad97421fb1fb | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
antbig | 0:ad97421fb1fb | 12 | * processor based microcontrollers. This file can be freely distributed |
antbig | 0:ad97421fb1fb | 13 | * within development tools that are supporting such ARM based processors. |
antbig | 0:ad97421fb1fb | 14 | * |
antbig | 0:ad97421fb1fb | 15 | * @par |
antbig | 0:ad97421fb1fb | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
antbig | 0:ad97421fb1fb | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
antbig | 0:ad97421fb1fb | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
antbig | 0:ad97421fb1fb | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
antbig | 0:ad97421fb1fb | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
antbig | 0:ad97421fb1fb | 21 | * |
antbig | 0:ad97421fb1fb | 22 | ******************************************************************************/ |
antbig | 0:ad97421fb1fb | 23 | |
antbig | 0:ad97421fb1fb | 24 | #ifndef __CORE_CMFUNC_H |
antbig | 0:ad97421fb1fb | 25 | #define __CORE_CMFUNC_H |
antbig | 0:ad97421fb1fb | 26 | |
antbig | 0:ad97421fb1fb | 27 | |
antbig | 0:ad97421fb1fb | 28 | /* ########################### Core Function Access ########################### */ |
antbig | 0:ad97421fb1fb | 29 | /** \ingroup CMSIS_Core_FunctionInterface |
antbig | 0:ad97421fb1fb | 30 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
antbig | 0:ad97421fb1fb | 31 | @{ |
antbig | 0:ad97421fb1fb | 32 | */ |
antbig | 0:ad97421fb1fb | 33 | |
antbig | 0:ad97421fb1fb | 34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
antbig | 0:ad97421fb1fb | 35 | /* ARM armcc specific functions */ |
antbig | 0:ad97421fb1fb | 36 | |
antbig | 0:ad97421fb1fb | 37 | #if (__ARMCC_VERSION < 400677) |
antbig | 0:ad97421fb1fb | 38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
antbig | 0:ad97421fb1fb | 39 | #endif |
antbig | 0:ad97421fb1fb | 40 | |
antbig | 0:ad97421fb1fb | 41 | /* intrinsic void __enable_irq(); */ |
antbig | 0:ad97421fb1fb | 42 | /* intrinsic void __disable_irq(); */ |
antbig | 0:ad97421fb1fb | 43 | |
antbig | 0:ad97421fb1fb | 44 | /** \brief Get Control Register |
antbig | 0:ad97421fb1fb | 45 | |
antbig | 0:ad97421fb1fb | 46 | This function returns the content of the Control Register. |
antbig | 0:ad97421fb1fb | 47 | |
antbig | 0:ad97421fb1fb | 48 | \return Control Register value |
antbig | 0:ad97421fb1fb | 49 | */ |
antbig | 0:ad97421fb1fb | 50 | static __INLINE uint32_t __get_CONTROL(void) |
antbig | 0:ad97421fb1fb | 51 | { |
antbig | 0:ad97421fb1fb | 52 | register uint32_t __regControl __ASM("control"); |
antbig | 0:ad97421fb1fb | 53 | return(__regControl); |
antbig | 0:ad97421fb1fb | 54 | } |
antbig | 0:ad97421fb1fb | 55 | |
antbig | 0:ad97421fb1fb | 56 | |
antbig | 0:ad97421fb1fb | 57 | /** \brief Set Control Register |
antbig | 0:ad97421fb1fb | 58 | |
antbig | 0:ad97421fb1fb | 59 | This function writes the given value to the Control Register. |
antbig | 0:ad97421fb1fb | 60 | |
antbig | 0:ad97421fb1fb | 61 | \param [in] control Control Register value to set |
antbig | 0:ad97421fb1fb | 62 | */ |
antbig | 0:ad97421fb1fb | 63 | static __INLINE void __set_CONTROL(uint32_t control) |
antbig | 0:ad97421fb1fb | 64 | { |
antbig | 0:ad97421fb1fb | 65 | register uint32_t __regControl __ASM("control"); |
antbig | 0:ad97421fb1fb | 66 | __regControl = control; |
antbig | 0:ad97421fb1fb | 67 | } |
antbig | 0:ad97421fb1fb | 68 | |
antbig | 0:ad97421fb1fb | 69 | |
antbig | 0:ad97421fb1fb | 70 | /** \brief Get IPSR Register |
antbig | 0:ad97421fb1fb | 71 | |
antbig | 0:ad97421fb1fb | 72 | This function returns the content of the IPSR Register. |
antbig | 0:ad97421fb1fb | 73 | |
antbig | 0:ad97421fb1fb | 74 | \return IPSR Register value |
antbig | 0:ad97421fb1fb | 75 | */ |
antbig | 0:ad97421fb1fb | 76 | static __INLINE uint32_t __get_IPSR(void) |
antbig | 0:ad97421fb1fb | 77 | { |
antbig | 0:ad97421fb1fb | 78 | register uint32_t __regIPSR __ASM("ipsr"); |
antbig | 0:ad97421fb1fb | 79 | return(__regIPSR); |
antbig | 0:ad97421fb1fb | 80 | } |
antbig | 0:ad97421fb1fb | 81 | |
antbig | 0:ad97421fb1fb | 82 | |
antbig | 0:ad97421fb1fb | 83 | /** \brief Get APSR Register |
antbig | 0:ad97421fb1fb | 84 | |
antbig | 0:ad97421fb1fb | 85 | This function returns the content of the APSR Register. |
antbig | 0:ad97421fb1fb | 86 | |
antbig | 0:ad97421fb1fb | 87 | \return APSR Register value |
antbig | 0:ad97421fb1fb | 88 | */ |
antbig | 0:ad97421fb1fb | 89 | static __INLINE uint32_t __get_APSR(void) |
antbig | 0:ad97421fb1fb | 90 | { |
antbig | 0:ad97421fb1fb | 91 | register uint32_t __regAPSR __ASM("apsr"); |
antbig | 0:ad97421fb1fb | 92 | return(__regAPSR); |
antbig | 0:ad97421fb1fb | 93 | } |
antbig | 0:ad97421fb1fb | 94 | |
antbig | 0:ad97421fb1fb | 95 | |
antbig | 0:ad97421fb1fb | 96 | /** \brief Get xPSR Register |
antbig | 0:ad97421fb1fb | 97 | |
antbig | 0:ad97421fb1fb | 98 | This function returns the content of the xPSR Register. |
antbig | 0:ad97421fb1fb | 99 | |
antbig | 0:ad97421fb1fb | 100 | \return xPSR Register value |
antbig | 0:ad97421fb1fb | 101 | */ |
antbig | 0:ad97421fb1fb | 102 | static __INLINE uint32_t __get_xPSR(void) |
antbig | 0:ad97421fb1fb | 103 | { |
antbig | 0:ad97421fb1fb | 104 | register uint32_t __regXPSR __ASM("xpsr"); |
antbig | 0:ad97421fb1fb | 105 | return(__regXPSR); |
antbig | 0:ad97421fb1fb | 106 | } |
antbig | 0:ad97421fb1fb | 107 | |
antbig | 0:ad97421fb1fb | 108 | |
antbig | 0:ad97421fb1fb | 109 | /** \brief Get Process Stack Pointer |
antbig | 0:ad97421fb1fb | 110 | |
antbig | 0:ad97421fb1fb | 111 | This function returns the current value of the Process Stack Pointer (PSP). |
antbig | 0:ad97421fb1fb | 112 | |
antbig | 0:ad97421fb1fb | 113 | \return PSP Register value |
antbig | 0:ad97421fb1fb | 114 | */ |
antbig | 0:ad97421fb1fb | 115 | static __INLINE uint32_t __get_PSP(void) |
antbig | 0:ad97421fb1fb | 116 | { |
antbig | 0:ad97421fb1fb | 117 | register uint32_t __regProcessStackPointer __ASM("psp"); |
antbig | 0:ad97421fb1fb | 118 | return(__regProcessStackPointer); |
antbig | 0:ad97421fb1fb | 119 | } |
antbig | 0:ad97421fb1fb | 120 | |
antbig | 0:ad97421fb1fb | 121 | |
antbig | 0:ad97421fb1fb | 122 | /** \brief Set Process Stack Pointer |
antbig | 0:ad97421fb1fb | 123 | |
antbig | 0:ad97421fb1fb | 124 | This function assigns the given value to the Process Stack Pointer (PSP). |
antbig | 0:ad97421fb1fb | 125 | |
antbig | 0:ad97421fb1fb | 126 | \param [in] topOfProcStack Process Stack Pointer value to set |
antbig | 0:ad97421fb1fb | 127 | */ |
antbig | 0:ad97421fb1fb | 128 | static __INLINE void __set_PSP(uint32_t topOfProcStack) |
antbig | 0:ad97421fb1fb | 129 | { |
antbig | 0:ad97421fb1fb | 130 | register uint32_t __regProcessStackPointer __ASM("psp"); |
antbig | 0:ad97421fb1fb | 131 | __regProcessStackPointer = topOfProcStack; |
antbig | 0:ad97421fb1fb | 132 | } |
antbig | 0:ad97421fb1fb | 133 | |
antbig | 0:ad97421fb1fb | 134 | |
antbig | 0:ad97421fb1fb | 135 | /** \brief Get Main Stack Pointer |
antbig | 0:ad97421fb1fb | 136 | |
antbig | 0:ad97421fb1fb | 137 | This function returns the current value of the Main Stack Pointer (MSP). |
antbig | 0:ad97421fb1fb | 138 | |
antbig | 0:ad97421fb1fb | 139 | \return MSP Register value |
antbig | 0:ad97421fb1fb | 140 | */ |
antbig | 0:ad97421fb1fb | 141 | static __INLINE uint32_t __get_MSP(void) |
antbig | 0:ad97421fb1fb | 142 | { |
antbig | 0:ad97421fb1fb | 143 | register uint32_t __regMainStackPointer __ASM("msp"); |
antbig | 0:ad97421fb1fb | 144 | return(__regMainStackPointer); |
antbig | 0:ad97421fb1fb | 145 | } |
antbig | 0:ad97421fb1fb | 146 | |
antbig | 0:ad97421fb1fb | 147 | |
antbig | 0:ad97421fb1fb | 148 | /** \brief Set Main Stack Pointer |
antbig | 0:ad97421fb1fb | 149 | |
antbig | 0:ad97421fb1fb | 150 | This function assigns the given value to the Main Stack Pointer (MSP). |
antbig | 0:ad97421fb1fb | 151 | |
antbig | 0:ad97421fb1fb | 152 | \param [in] topOfMainStack Main Stack Pointer value to set |
antbig | 0:ad97421fb1fb | 153 | */ |
antbig | 0:ad97421fb1fb | 154 | static __INLINE void __set_MSP(uint32_t topOfMainStack) |
antbig | 0:ad97421fb1fb | 155 | { |
antbig | 0:ad97421fb1fb | 156 | register uint32_t __regMainStackPointer __ASM("msp"); |
antbig | 0:ad97421fb1fb | 157 | __regMainStackPointer = topOfMainStack; |
antbig | 0:ad97421fb1fb | 158 | } |
antbig | 0:ad97421fb1fb | 159 | |
antbig | 0:ad97421fb1fb | 160 | |
antbig | 0:ad97421fb1fb | 161 | /** \brief Get Priority Mask |
antbig | 0:ad97421fb1fb | 162 | |
antbig | 0:ad97421fb1fb | 163 | This function returns the current state of the priority mask bit from the Priority Mask Register. |
antbig | 0:ad97421fb1fb | 164 | |
antbig | 0:ad97421fb1fb | 165 | \return Priority Mask value |
antbig | 0:ad97421fb1fb | 166 | */ |
antbig | 0:ad97421fb1fb | 167 | static __INLINE uint32_t __get_PRIMASK(void) |
antbig | 0:ad97421fb1fb | 168 | { |
antbig | 0:ad97421fb1fb | 169 | register uint32_t __regPriMask __ASM("primask"); |
antbig | 0:ad97421fb1fb | 170 | return(__regPriMask); |
antbig | 0:ad97421fb1fb | 171 | } |
antbig | 0:ad97421fb1fb | 172 | |
antbig | 0:ad97421fb1fb | 173 | |
antbig | 0:ad97421fb1fb | 174 | /** \brief Set Priority Mask |
antbig | 0:ad97421fb1fb | 175 | |
antbig | 0:ad97421fb1fb | 176 | This function assigns the given value to the Priority Mask Register. |
antbig | 0:ad97421fb1fb | 177 | |
antbig | 0:ad97421fb1fb | 178 | \param [in] priMask Priority Mask |
antbig | 0:ad97421fb1fb | 179 | */ |
antbig | 0:ad97421fb1fb | 180 | static __INLINE void __set_PRIMASK(uint32_t priMask) |
antbig | 0:ad97421fb1fb | 181 | { |
antbig | 0:ad97421fb1fb | 182 | register uint32_t __regPriMask __ASM("primask"); |
antbig | 0:ad97421fb1fb | 183 | __regPriMask = (priMask); |
antbig | 0:ad97421fb1fb | 184 | } |
antbig | 0:ad97421fb1fb | 185 | |
antbig | 0:ad97421fb1fb | 186 | |
antbig | 0:ad97421fb1fb | 187 | #if (__CORTEX_M >= 0x03) |
antbig | 0:ad97421fb1fb | 188 | |
antbig | 0:ad97421fb1fb | 189 | /** \brief Enable FIQ |
antbig | 0:ad97421fb1fb | 190 | |
antbig | 0:ad97421fb1fb | 191 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
antbig | 0:ad97421fb1fb | 192 | Can only be executed in Privileged modes. |
antbig | 0:ad97421fb1fb | 193 | */ |
antbig | 0:ad97421fb1fb | 194 | #define __enable_fault_irq __enable_fiq |
antbig | 0:ad97421fb1fb | 195 | |
antbig | 0:ad97421fb1fb | 196 | |
antbig | 0:ad97421fb1fb | 197 | /** \brief Disable FIQ |
antbig | 0:ad97421fb1fb | 198 | |
antbig | 0:ad97421fb1fb | 199 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
antbig | 0:ad97421fb1fb | 200 | Can only be executed in Privileged modes. |
antbig | 0:ad97421fb1fb | 201 | */ |
antbig | 0:ad97421fb1fb | 202 | #define __disable_fault_irq __disable_fiq |
antbig | 0:ad97421fb1fb | 203 | |
antbig | 0:ad97421fb1fb | 204 | |
antbig | 0:ad97421fb1fb | 205 | /** \brief Get Base Priority |
antbig | 0:ad97421fb1fb | 206 | |
antbig | 0:ad97421fb1fb | 207 | This function returns the current value of the Base Priority register. |
antbig | 0:ad97421fb1fb | 208 | |
antbig | 0:ad97421fb1fb | 209 | \return Base Priority register value |
antbig | 0:ad97421fb1fb | 210 | */ |
antbig | 0:ad97421fb1fb | 211 | static __INLINE uint32_t __get_BASEPRI(void) |
antbig | 0:ad97421fb1fb | 212 | { |
antbig | 0:ad97421fb1fb | 213 | register uint32_t __regBasePri __ASM("basepri"); |
antbig | 0:ad97421fb1fb | 214 | return(__regBasePri); |
antbig | 0:ad97421fb1fb | 215 | } |
antbig | 0:ad97421fb1fb | 216 | |
antbig | 0:ad97421fb1fb | 217 | |
antbig | 0:ad97421fb1fb | 218 | /** \brief Set Base Priority |
antbig | 0:ad97421fb1fb | 219 | |
antbig | 0:ad97421fb1fb | 220 | This function assigns the given value to the Base Priority register. |
antbig | 0:ad97421fb1fb | 221 | |
antbig | 0:ad97421fb1fb | 222 | \param [in] basePri Base Priority value to set |
antbig | 0:ad97421fb1fb | 223 | */ |
antbig | 0:ad97421fb1fb | 224 | static __INLINE void __set_BASEPRI(uint32_t basePri) |
antbig | 0:ad97421fb1fb | 225 | { |
antbig | 0:ad97421fb1fb | 226 | register uint32_t __regBasePri __ASM("basepri"); |
antbig | 0:ad97421fb1fb | 227 | __regBasePri = (basePri & 0xff); |
antbig | 0:ad97421fb1fb | 228 | } |
antbig | 0:ad97421fb1fb | 229 | |
antbig | 0:ad97421fb1fb | 230 | |
antbig | 0:ad97421fb1fb | 231 | /** \brief Get Fault Mask |
antbig | 0:ad97421fb1fb | 232 | |
antbig | 0:ad97421fb1fb | 233 | This function returns the current value of the Fault Mask register. |
antbig | 0:ad97421fb1fb | 234 | |
antbig | 0:ad97421fb1fb | 235 | \return Fault Mask register value |
antbig | 0:ad97421fb1fb | 236 | */ |
antbig | 0:ad97421fb1fb | 237 | static __INLINE uint32_t __get_FAULTMASK(void) |
antbig | 0:ad97421fb1fb | 238 | { |
antbig | 0:ad97421fb1fb | 239 | register uint32_t __regFaultMask __ASM("faultmask"); |
antbig | 0:ad97421fb1fb | 240 | return(__regFaultMask); |
antbig | 0:ad97421fb1fb | 241 | } |
antbig | 0:ad97421fb1fb | 242 | |
antbig | 0:ad97421fb1fb | 243 | |
antbig | 0:ad97421fb1fb | 244 | /** \brief Set Fault Mask |
antbig | 0:ad97421fb1fb | 245 | |
antbig | 0:ad97421fb1fb | 246 | This function assigns the given value to the Fault Mask register. |
antbig | 0:ad97421fb1fb | 247 | |
antbig | 0:ad97421fb1fb | 248 | \param [in] faultMask Fault Mask value to set |
antbig | 0:ad97421fb1fb | 249 | */ |
antbig | 0:ad97421fb1fb | 250 | static __INLINE void __set_FAULTMASK(uint32_t faultMask) |
antbig | 0:ad97421fb1fb | 251 | { |
antbig | 0:ad97421fb1fb | 252 | register uint32_t __regFaultMask __ASM("faultmask"); |
antbig | 0:ad97421fb1fb | 253 | __regFaultMask = (faultMask & (uint32_t)1); |
antbig | 0:ad97421fb1fb | 254 | } |
antbig | 0:ad97421fb1fb | 255 | |
antbig | 0:ad97421fb1fb | 256 | #endif /* (__CORTEX_M >= 0x03) */ |
antbig | 0:ad97421fb1fb | 257 | |
antbig | 0:ad97421fb1fb | 258 | |
antbig | 0:ad97421fb1fb | 259 | #if (__CORTEX_M == 0x04) |
antbig | 0:ad97421fb1fb | 260 | |
antbig | 0:ad97421fb1fb | 261 | /** \brief Get FPSCR |
antbig | 0:ad97421fb1fb | 262 | |
antbig | 0:ad97421fb1fb | 263 | This function returns the current value of the Floating Point Status/Control register. |
antbig | 0:ad97421fb1fb | 264 | |
antbig | 0:ad97421fb1fb | 265 | \return Floating Point Status/Control register value |
antbig | 0:ad97421fb1fb | 266 | */ |
antbig | 0:ad97421fb1fb | 267 | static __INLINE uint32_t __get_FPSCR(void) |
antbig | 0:ad97421fb1fb | 268 | { |
antbig | 0:ad97421fb1fb | 269 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
antbig | 0:ad97421fb1fb | 270 | register uint32_t __regfpscr __ASM("fpscr"); |
antbig | 0:ad97421fb1fb | 271 | return(__regfpscr); |
antbig | 0:ad97421fb1fb | 272 | #else |
antbig | 0:ad97421fb1fb | 273 | return(0); |
antbig | 0:ad97421fb1fb | 274 | #endif |
antbig | 0:ad97421fb1fb | 275 | } |
antbig | 0:ad97421fb1fb | 276 | |
antbig | 0:ad97421fb1fb | 277 | |
antbig | 0:ad97421fb1fb | 278 | /** \brief Set FPSCR |
antbig | 0:ad97421fb1fb | 279 | |
antbig | 0:ad97421fb1fb | 280 | This function assigns the given value to the Floating Point Status/Control register. |
antbig | 0:ad97421fb1fb | 281 | |
antbig | 0:ad97421fb1fb | 282 | \param [in] fpscr Floating Point Status/Control value to set |
antbig | 0:ad97421fb1fb | 283 | */ |
antbig | 0:ad97421fb1fb | 284 | static __INLINE void __set_FPSCR(uint32_t fpscr) |
antbig | 0:ad97421fb1fb | 285 | { |
antbig | 0:ad97421fb1fb | 286 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
antbig | 0:ad97421fb1fb | 287 | register uint32_t __regfpscr __ASM("fpscr"); |
antbig | 0:ad97421fb1fb | 288 | __regfpscr = (fpscr); |
antbig | 0:ad97421fb1fb | 289 | #endif |
antbig | 0:ad97421fb1fb | 290 | } |
antbig | 0:ad97421fb1fb | 291 | |
antbig | 0:ad97421fb1fb | 292 | #endif /* (__CORTEX_M == 0x04) */ |
antbig | 0:ad97421fb1fb | 293 | |
antbig | 0:ad97421fb1fb | 294 | |
antbig | 0:ad97421fb1fb | 295 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ |
antbig | 0:ad97421fb1fb | 296 | /* IAR iccarm specific functions */ |
antbig | 0:ad97421fb1fb | 297 | |
antbig | 0:ad97421fb1fb | 298 | #include <cmsis_iar.h> |
antbig | 0:ad97421fb1fb | 299 | |
antbig | 0:ad97421fb1fb | 300 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ |
antbig | 0:ad97421fb1fb | 301 | /* GNU gcc specific functions */ |
antbig | 0:ad97421fb1fb | 302 | |
antbig | 0:ad97421fb1fb | 303 | /** \brief Enable IRQ Interrupts |
antbig | 0:ad97421fb1fb | 304 | |
antbig | 0:ad97421fb1fb | 305 | This function enables IRQ interrupts by clearing the I-bit in the CPSR. |
antbig | 0:ad97421fb1fb | 306 | Can only be executed in Privileged modes. |
antbig | 0:ad97421fb1fb | 307 | */ |
antbig | 0:ad97421fb1fb | 308 | __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) |
antbig | 0:ad97421fb1fb | 309 | { |
antbig | 0:ad97421fb1fb | 310 | __ASM volatile ("cpsie i"); |
antbig | 0:ad97421fb1fb | 311 | } |
antbig | 0:ad97421fb1fb | 312 | |
antbig | 0:ad97421fb1fb | 313 | |
antbig | 0:ad97421fb1fb | 314 | /** \brief Disable IRQ Interrupts |
antbig | 0:ad97421fb1fb | 315 | |
antbig | 0:ad97421fb1fb | 316 | This function disables IRQ interrupts by setting the I-bit in the CPSR. |
antbig | 0:ad97421fb1fb | 317 | Can only be executed in Privileged modes. |
antbig | 0:ad97421fb1fb | 318 | */ |
antbig | 0:ad97421fb1fb | 319 | __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) |
antbig | 0:ad97421fb1fb | 320 | { |
antbig | 0:ad97421fb1fb | 321 | __ASM volatile ("cpsid i"); |
antbig | 0:ad97421fb1fb | 322 | } |
antbig | 0:ad97421fb1fb | 323 | |
antbig | 0:ad97421fb1fb | 324 | |
antbig | 0:ad97421fb1fb | 325 | /** \brief Get Control Register |
antbig | 0:ad97421fb1fb | 326 | |
antbig | 0:ad97421fb1fb | 327 | This function returns the content of the Control Register. |
antbig | 0:ad97421fb1fb | 328 | |
antbig | 0:ad97421fb1fb | 329 | \return Control Register value |
antbig | 0:ad97421fb1fb | 330 | */ |
antbig | 0:ad97421fb1fb | 331 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) |
antbig | 0:ad97421fb1fb | 332 | { |
antbig | 0:ad97421fb1fb | 333 | uint32_t result; |
antbig | 0:ad97421fb1fb | 334 | |
antbig | 0:ad97421fb1fb | 335 | __ASM volatile ("MRS %0, control" : "=r" (result) ); |
antbig | 0:ad97421fb1fb | 336 | return(result); |
antbig | 0:ad97421fb1fb | 337 | } |
antbig | 0:ad97421fb1fb | 338 | |
antbig | 0:ad97421fb1fb | 339 | |
antbig | 0:ad97421fb1fb | 340 | /** \brief Set Control Register |
antbig | 0:ad97421fb1fb | 341 | |
antbig | 0:ad97421fb1fb | 342 | This function writes the given value to the Control Register. |
antbig | 0:ad97421fb1fb | 343 | |
antbig | 0:ad97421fb1fb | 344 | \param [in] control Control Register value to set |
antbig | 0:ad97421fb1fb | 345 | */ |
antbig | 0:ad97421fb1fb | 346 | __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) |
antbig | 0:ad97421fb1fb | 347 | { |
antbig | 0:ad97421fb1fb | 348 | __ASM volatile ("MSR control, %0" : : "r" (control) ); |
antbig | 0:ad97421fb1fb | 349 | } |
antbig | 0:ad97421fb1fb | 350 | |
antbig | 0:ad97421fb1fb | 351 | |
antbig | 0:ad97421fb1fb | 352 | /** \brief Get IPSR Register |
antbig | 0:ad97421fb1fb | 353 | |
antbig | 0:ad97421fb1fb | 354 | This function returns the content of the IPSR Register. |
antbig | 0:ad97421fb1fb | 355 | |
antbig | 0:ad97421fb1fb | 356 | \return IPSR Register value |
antbig | 0:ad97421fb1fb | 357 | */ |
antbig | 0:ad97421fb1fb | 358 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) |
antbig | 0:ad97421fb1fb | 359 | { |
antbig | 0:ad97421fb1fb | 360 | uint32_t result; |
antbig | 0:ad97421fb1fb | 361 | |
antbig | 0:ad97421fb1fb | 362 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); |
antbig | 0:ad97421fb1fb | 363 | return(result); |
antbig | 0:ad97421fb1fb | 364 | } |
antbig | 0:ad97421fb1fb | 365 | |
antbig | 0:ad97421fb1fb | 366 | |
antbig | 0:ad97421fb1fb | 367 | /** \brief Get APSR Register |
antbig | 0:ad97421fb1fb | 368 | |
antbig | 0:ad97421fb1fb | 369 | This function returns the content of the APSR Register. |
antbig | 0:ad97421fb1fb | 370 | |
antbig | 0:ad97421fb1fb | 371 | \return APSR Register value |
antbig | 0:ad97421fb1fb | 372 | */ |
antbig | 0:ad97421fb1fb | 373 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) |
antbig | 0:ad97421fb1fb | 374 | { |
antbig | 0:ad97421fb1fb | 375 | uint32_t result; |
antbig | 0:ad97421fb1fb | 376 | |
antbig | 0:ad97421fb1fb | 377 | __ASM volatile ("MRS %0, apsr" : "=r" (result) ); |
antbig | 0:ad97421fb1fb | 378 | return(result); |
antbig | 0:ad97421fb1fb | 379 | } |
antbig | 0:ad97421fb1fb | 380 | |
antbig | 0:ad97421fb1fb | 381 | |
antbig | 0:ad97421fb1fb | 382 | /** \brief Get xPSR Register |
antbig | 0:ad97421fb1fb | 383 | |
antbig | 0:ad97421fb1fb | 384 | This function returns the content of the xPSR Register. |
antbig | 0:ad97421fb1fb | 385 | |
antbig | 0:ad97421fb1fb | 386 | \return xPSR Register value |
antbig | 0:ad97421fb1fb | 387 | */ |
antbig | 0:ad97421fb1fb | 388 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) |
antbig | 0:ad97421fb1fb | 389 | { |
antbig | 0:ad97421fb1fb | 390 | uint32_t result; |
antbig | 0:ad97421fb1fb | 391 | |
antbig | 0:ad97421fb1fb | 392 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); |
antbig | 0:ad97421fb1fb | 393 | return(result); |
antbig | 0:ad97421fb1fb | 394 | } |
antbig | 0:ad97421fb1fb | 395 | |
antbig | 0:ad97421fb1fb | 396 | |
antbig | 0:ad97421fb1fb | 397 | /** \brief Get Process Stack Pointer |
antbig | 0:ad97421fb1fb | 398 | |
antbig | 0:ad97421fb1fb | 399 | This function returns the current value of the Process Stack Pointer (PSP). |
antbig | 0:ad97421fb1fb | 400 | |
antbig | 0:ad97421fb1fb | 401 | \return PSP Register value |
antbig | 0:ad97421fb1fb | 402 | */ |
antbig | 0:ad97421fb1fb | 403 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) |
antbig | 0:ad97421fb1fb | 404 | { |
antbig | 0:ad97421fb1fb | 405 | register uint32_t result; |
antbig | 0:ad97421fb1fb | 406 | |
antbig | 0:ad97421fb1fb | 407 | __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); |
antbig | 0:ad97421fb1fb | 408 | return(result); |
antbig | 0:ad97421fb1fb | 409 | } |
antbig | 0:ad97421fb1fb | 410 | |
antbig | 0:ad97421fb1fb | 411 | |
antbig | 0:ad97421fb1fb | 412 | /** \brief Set Process Stack Pointer |
antbig | 0:ad97421fb1fb | 413 | |
antbig | 0:ad97421fb1fb | 414 | This function assigns the given value to the Process Stack Pointer (PSP). |
antbig | 0:ad97421fb1fb | 415 | |
antbig | 0:ad97421fb1fb | 416 | \param [in] topOfProcStack Process Stack Pointer value to set |
antbig | 0:ad97421fb1fb | 417 | */ |
antbig | 0:ad97421fb1fb | 418 | __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) |
antbig | 0:ad97421fb1fb | 419 | { |
antbig | 0:ad97421fb1fb | 420 | __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); |
antbig | 0:ad97421fb1fb | 421 | } |
antbig | 0:ad97421fb1fb | 422 | |
antbig | 0:ad97421fb1fb | 423 | |
antbig | 0:ad97421fb1fb | 424 | /** \brief Get Main Stack Pointer |
antbig | 0:ad97421fb1fb | 425 | |
antbig | 0:ad97421fb1fb | 426 | This function returns the current value of the Main Stack Pointer (MSP). |
antbig | 0:ad97421fb1fb | 427 | |
antbig | 0:ad97421fb1fb | 428 | \return MSP Register value |
antbig | 0:ad97421fb1fb | 429 | */ |
antbig | 0:ad97421fb1fb | 430 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) |
antbig | 0:ad97421fb1fb | 431 | { |
antbig | 0:ad97421fb1fb | 432 | register uint32_t result; |
antbig | 0:ad97421fb1fb | 433 | |
antbig | 0:ad97421fb1fb | 434 | __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); |
antbig | 0:ad97421fb1fb | 435 | return(result); |
antbig | 0:ad97421fb1fb | 436 | } |
antbig | 0:ad97421fb1fb | 437 | |
antbig | 0:ad97421fb1fb | 438 | |
antbig | 0:ad97421fb1fb | 439 | /** \brief Set Main Stack Pointer |
antbig | 0:ad97421fb1fb | 440 | |
antbig | 0:ad97421fb1fb | 441 | This function assigns the given value to the Main Stack Pointer (MSP). |
antbig | 0:ad97421fb1fb | 442 | |
antbig | 0:ad97421fb1fb | 443 | \param [in] topOfMainStack Main Stack Pointer value to set |
antbig | 0:ad97421fb1fb | 444 | */ |
antbig | 0:ad97421fb1fb | 445 | __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) |
antbig | 0:ad97421fb1fb | 446 | { |
antbig | 0:ad97421fb1fb | 447 | __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); |
antbig | 0:ad97421fb1fb | 448 | } |
antbig | 0:ad97421fb1fb | 449 | |
antbig | 0:ad97421fb1fb | 450 | |
antbig | 0:ad97421fb1fb | 451 | /** \brief Get Priority Mask |
antbig | 0:ad97421fb1fb | 452 | |
antbig | 0:ad97421fb1fb | 453 | This function returns the current state of the priority mask bit from the Priority Mask Register. |
antbig | 0:ad97421fb1fb | 454 | |
antbig | 0:ad97421fb1fb | 455 | \return Priority Mask value |
antbig | 0:ad97421fb1fb | 456 | */ |
antbig | 0:ad97421fb1fb | 457 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) |
antbig | 0:ad97421fb1fb | 458 | { |
antbig | 0:ad97421fb1fb | 459 | uint32_t result; |
antbig | 0:ad97421fb1fb | 460 | |
antbig | 0:ad97421fb1fb | 461 | __ASM volatile ("MRS %0, primask" : "=r" (result) ); |
antbig | 0:ad97421fb1fb | 462 | return(result); |
antbig | 0:ad97421fb1fb | 463 | } |
antbig | 0:ad97421fb1fb | 464 | |
antbig | 0:ad97421fb1fb | 465 | |
antbig | 0:ad97421fb1fb | 466 | /** \brief Set Priority Mask |
antbig | 0:ad97421fb1fb | 467 | |
antbig | 0:ad97421fb1fb | 468 | This function assigns the given value to the Priority Mask Register. |
antbig | 0:ad97421fb1fb | 469 | |
antbig | 0:ad97421fb1fb | 470 | \param [in] priMask Priority Mask |
antbig | 0:ad97421fb1fb | 471 | */ |
antbig | 0:ad97421fb1fb | 472 | __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) |
antbig | 0:ad97421fb1fb | 473 | { |
antbig | 0:ad97421fb1fb | 474 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); |
antbig | 0:ad97421fb1fb | 475 | } |
antbig | 0:ad97421fb1fb | 476 | |
antbig | 0:ad97421fb1fb | 477 | |
antbig | 0:ad97421fb1fb | 478 | #if (__CORTEX_M >= 0x03) |
antbig | 0:ad97421fb1fb | 479 | |
antbig | 0:ad97421fb1fb | 480 | /** \brief Enable FIQ |
antbig | 0:ad97421fb1fb | 481 | |
antbig | 0:ad97421fb1fb | 482 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
antbig | 0:ad97421fb1fb | 483 | Can only be executed in Privileged modes. |
antbig | 0:ad97421fb1fb | 484 | */ |
antbig | 0:ad97421fb1fb | 485 | __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) |
antbig | 0:ad97421fb1fb | 486 | { |
antbig | 0:ad97421fb1fb | 487 | __ASM volatile ("cpsie f"); |
antbig | 0:ad97421fb1fb | 488 | } |
antbig | 0:ad97421fb1fb | 489 | |
antbig | 0:ad97421fb1fb | 490 | |
antbig | 0:ad97421fb1fb | 491 | /** \brief Disable FIQ |
antbig | 0:ad97421fb1fb | 492 | |
antbig | 0:ad97421fb1fb | 493 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
antbig | 0:ad97421fb1fb | 494 | Can only be executed in Privileged modes. |
antbig | 0:ad97421fb1fb | 495 | */ |
antbig | 0:ad97421fb1fb | 496 | __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) |
antbig | 0:ad97421fb1fb | 497 | { |
antbig | 0:ad97421fb1fb | 498 | __ASM volatile ("cpsid f"); |
antbig | 0:ad97421fb1fb | 499 | } |
antbig | 0:ad97421fb1fb | 500 | |
antbig | 0:ad97421fb1fb | 501 | |
antbig | 0:ad97421fb1fb | 502 | /** \brief Get Base Priority |
antbig | 0:ad97421fb1fb | 503 | |
antbig | 0:ad97421fb1fb | 504 | This function returns the current value of the Base Priority register. |
antbig | 0:ad97421fb1fb | 505 | |
antbig | 0:ad97421fb1fb | 506 | \return Base Priority register value |
antbig | 0:ad97421fb1fb | 507 | */ |
antbig | 0:ad97421fb1fb | 508 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) |
antbig | 0:ad97421fb1fb | 509 | { |
antbig | 0:ad97421fb1fb | 510 | uint32_t result; |
antbig | 0:ad97421fb1fb | 511 | |
antbig | 0:ad97421fb1fb | 512 | __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); |
antbig | 0:ad97421fb1fb | 513 | return(result); |
antbig | 0:ad97421fb1fb | 514 | } |
antbig | 0:ad97421fb1fb | 515 | |
antbig | 0:ad97421fb1fb | 516 | |
antbig | 0:ad97421fb1fb | 517 | /** \brief Set Base Priority |
antbig | 0:ad97421fb1fb | 518 | |
antbig | 0:ad97421fb1fb | 519 | This function assigns the given value to the Base Priority register. |
antbig | 0:ad97421fb1fb | 520 | |
antbig | 0:ad97421fb1fb | 521 | \param [in] basePri Base Priority value to set |
antbig | 0:ad97421fb1fb | 522 | */ |
antbig | 0:ad97421fb1fb | 523 | __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) |
antbig | 0:ad97421fb1fb | 524 | { |
antbig | 0:ad97421fb1fb | 525 | __ASM volatile ("MSR basepri, %0" : : "r" (value) ); |
antbig | 0:ad97421fb1fb | 526 | } |
antbig | 0:ad97421fb1fb | 527 | |
antbig | 0:ad97421fb1fb | 528 | |
antbig | 0:ad97421fb1fb | 529 | /** \brief Get Fault Mask |
antbig | 0:ad97421fb1fb | 530 | |
antbig | 0:ad97421fb1fb | 531 | This function returns the current value of the Fault Mask register. |
antbig | 0:ad97421fb1fb | 532 | |
antbig | 0:ad97421fb1fb | 533 | \return Fault Mask register value |
antbig | 0:ad97421fb1fb | 534 | */ |
antbig | 0:ad97421fb1fb | 535 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) |
antbig | 0:ad97421fb1fb | 536 | { |
antbig | 0:ad97421fb1fb | 537 | uint32_t result; |
antbig | 0:ad97421fb1fb | 538 | |
antbig | 0:ad97421fb1fb | 539 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
antbig | 0:ad97421fb1fb | 540 | return(result); |
antbig | 0:ad97421fb1fb | 541 | } |
antbig | 0:ad97421fb1fb | 542 | |
antbig | 0:ad97421fb1fb | 543 | |
antbig | 0:ad97421fb1fb | 544 | /** \brief Set Fault Mask |
antbig | 0:ad97421fb1fb | 545 | |
antbig | 0:ad97421fb1fb | 546 | This function assigns the given value to the Fault Mask register. |
antbig | 0:ad97421fb1fb | 547 | |
antbig | 0:ad97421fb1fb | 548 | \param [in] faultMask Fault Mask value to set |
antbig | 0:ad97421fb1fb | 549 | */ |
antbig | 0:ad97421fb1fb | 550 | __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) |
antbig | 0:ad97421fb1fb | 551 | { |
antbig | 0:ad97421fb1fb | 552 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); |
antbig | 0:ad97421fb1fb | 553 | } |
antbig | 0:ad97421fb1fb | 554 | |
antbig | 0:ad97421fb1fb | 555 | #endif /* (__CORTEX_M >= 0x03) */ |
antbig | 0:ad97421fb1fb | 556 | |
antbig | 0:ad97421fb1fb | 557 | |
antbig | 0:ad97421fb1fb | 558 | #if (__CORTEX_M == 0x04) |
antbig | 0:ad97421fb1fb | 559 | |
antbig | 0:ad97421fb1fb | 560 | /** \brief Get FPSCR |
antbig | 0:ad97421fb1fb | 561 | |
antbig | 0:ad97421fb1fb | 562 | This function returns the current value of the Floating Point Status/Control register. |
antbig | 0:ad97421fb1fb | 563 | |
antbig | 0:ad97421fb1fb | 564 | \return Floating Point Status/Control register value |
antbig | 0:ad97421fb1fb | 565 | */ |
antbig | 0:ad97421fb1fb | 566 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) |
antbig | 0:ad97421fb1fb | 567 | { |
antbig | 0:ad97421fb1fb | 568 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
antbig | 0:ad97421fb1fb | 569 | uint32_t result; |
antbig | 0:ad97421fb1fb | 570 | |
antbig | 0:ad97421fb1fb | 571 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); |
antbig | 0:ad97421fb1fb | 572 | return(result); |
antbig | 0:ad97421fb1fb | 573 | #else |
antbig | 0:ad97421fb1fb | 574 | return(0); |
antbig | 0:ad97421fb1fb | 575 | #endif |
antbig | 0:ad97421fb1fb | 576 | } |
antbig | 0:ad97421fb1fb | 577 | |
antbig | 0:ad97421fb1fb | 578 | |
antbig | 0:ad97421fb1fb | 579 | /** \brief Set FPSCR |
antbig | 0:ad97421fb1fb | 580 | |
antbig | 0:ad97421fb1fb | 581 | This function assigns the given value to the Floating Point Status/Control register. |
antbig | 0:ad97421fb1fb | 582 | |
antbig | 0:ad97421fb1fb | 583 | \param [in] fpscr Floating Point Status/Control value to set |
antbig | 0:ad97421fb1fb | 584 | */ |
antbig | 0:ad97421fb1fb | 585 | __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) |
antbig | 0:ad97421fb1fb | 586 | { |
antbig | 0:ad97421fb1fb | 587 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
antbig | 0:ad97421fb1fb | 588 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); |
antbig | 0:ad97421fb1fb | 589 | #endif |
antbig | 0:ad97421fb1fb | 590 | } |
antbig | 0:ad97421fb1fb | 591 | |
antbig | 0:ad97421fb1fb | 592 | #endif /* (__CORTEX_M == 0x04) */ |
antbig | 0:ad97421fb1fb | 593 | |
antbig | 0:ad97421fb1fb | 594 | |
antbig | 0:ad97421fb1fb | 595 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ |
antbig | 0:ad97421fb1fb | 596 | /* TASKING carm specific functions */ |
antbig | 0:ad97421fb1fb | 597 | |
antbig | 0:ad97421fb1fb | 598 | /* |
antbig | 0:ad97421fb1fb | 599 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
antbig | 0:ad97421fb1fb | 600 | * Please use "carm -?i" to get an up to date list of all instrinsics, |
antbig | 0:ad97421fb1fb | 601 | * Including the CMSIS ones. |
antbig | 0:ad97421fb1fb | 602 | */ |
antbig | 0:ad97421fb1fb | 603 | |
antbig | 0:ad97421fb1fb | 604 | #endif |
antbig | 0:ad97421fb1fb | 605 | |
antbig | 0:ad97421fb1fb | 606 | /*@} end of CMSIS_Core_RegAccFunctions */ |
antbig | 0:ad97421fb1fb | 607 | |
antbig | 0:ad97421fb1fb | 608 | |
antbig | 0:ad97421fb1fb | 609 | #endif /* __CORE_CMFUNC_H */ |