CQ Publishing / Mbed 2 deprecated tg_201410s8_AD7714

Transistor Gijutsu, October 2014, Special Features Chapter 8，Software of the thermistor thermometer of 0.001 ° resolution， トランジスタ技術2014年10月号　特集第8章のソフトウェア　0.001℃分解能で気配もキャッチ「超敏感肌温度計」

Dependencies:   USBDevice mbed

Information

tg_201410s8_AD7714 トランジスタ技術 2014年 10月号 第8章のソフトウェア

Program for Section 8 in October. 2014 issue of the Transistor Gijutsu
(Japanese electronics magazine)

概要

このプログラムは、サーミスタの抵抗値変化をAD7714(24bitADC)で測定し、抵抗値を温度値に変換することで、0.001℃程度の分解能で温度変化を測定します。

ファイル

このソフトウエアは、次のファイルから構成されています。

  • AD7714.cpp - AD7714の内部レジスタを設定
  • Thermistor.cpp - サーミスタの抵抗値から温度値に変換
  • ExpAvr.cpp - 指数平均によるソフトウエアＬＰＦ
  • main.cpp - main()関数

詳細については、10月号の記事および上記ファイル中のコメントを参照してください。

USBDevice/USBDevice/USBHAL_STM32F4.cpp@0:de885a6da962, 2014-08-29 (annotated)

Committer:
Dance
Date:
Fri Aug 29 08:38:36 2014 +0000
Revision:
0:de885a6da962
Transistor Gijutsu, October 2014, Special Features Chapter 8; ????????2014?10??????8????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Dance 0:de885a6da962 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
Dance 0:de885a6da962 2 *
Dance 0:de885a6da962 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
Dance 0:de885a6da962 4 * and associated documentation files (the "Software"), to deal in the Software without
Dance 0:de885a6da962 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
Dance 0:de885a6da962 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
Dance 0:de885a6da962 7 * Software is furnished to do so, subject to the following conditions:
Dance 0:de885a6da962 8 *
Dance 0:de885a6da962 9 * The above copyright notice and this permission notice shall be included in all copies or
Dance 0:de885a6da962 10 * substantial portions of the Software.
Dance 0:de885a6da962 11 *
Dance 0:de885a6da962 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
Dance 0:de885a6da962 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
Dance 0:de885a6da962 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
Dance 0:de885a6da962 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Dance 0:de885a6da962 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Dance 0:de885a6da962 17 */
Dance 0:de885a6da962 18
Dance 0:de885a6da962 19 #if defined(TARGET_STM32F4XX)
Dance 0:de885a6da962 20
Dance 0:de885a6da962 21 #include "USBHAL.h"
Dance 0:de885a6da962 22 #include "USBRegs_STM32.h"
Dance 0:de885a6da962 23 #include "pinmap.h"
Dance 0:de885a6da962 24
Dance 0:de885a6da962 25 USBHAL * USBHAL::instance;
Dance 0:de885a6da962 26
Dance 0:de885a6da962 27 static volatile int epComplete = 0;
Dance 0:de885a6da962 28
Dance 0:de885a6da962 29 static uint32_t bufferEnd = 0;
Dance 0:de885a6da962 30 static const uint32_t rxFifoSize = 512;
Dance 0:de885a6da962 31 static uint32_t rxFifoCount = 0;
Dance 0:de885a6da962 32
Dance 0:de885a6da962 33 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
Dance 0:de885a6da962 34
Dance 0:de885a6da962 35 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
Dance 0:de885a6da962 36 return 0;
Dance 0:de885a6da962 37 }
Dance 0:de885a6da962 38
Dance 0:de885a6da962 39 USBHAL::USBHAL(void) {
Dance 0:de885a6da962 40 NVIC_DisableIRQ(OTG_FS_IRQn);
Dance 0:de885a6da962 41 epCallback[0] = &USBHAL::EP1_OUT_callback;
Dance 0:de885a6da962 42 epCallback[1] = &USBHAL::EP1_IN_callback;
Dance 0:de885a6da962 43 epCallback[2] = &USBHAL::EP2_OUT_callback;
Dance 0:de885a6da962 44 epCallback[3] = &USBHAL::EP2_IN_callback;
Dance 0:de885a6da962 45 epCallback[4] = &USBHAL::EP3_OUT_callback;
Dance 0:de885a6da962 46 epCallback[5] = &USBHAL::EP3_IN_callback;
Dance 0:de885a6da962 47
Dance 0:de885a6da962 48 // Enable power and clocking
Dance 0:de885a6da962 49 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
Dance 0:de885a6da962 50
Dance 0:de885a6da962 51 pin_function(PA_8, STM_PIN_DATA(2, 10));
Dance 0:de885a6da962 52 pin_function(PA_9, STM_PIN_DATA(0, 0));
Dance 0:de885a6da962 53 pin_function(PA_10, STM_PIN_DATA(2, 10));
Dance 0:de885a6da962 54 pin_function(PA_11, STM_PIN_DATA(2, 10));
Dance 0:de885a6da962 55 pin_function(PA_12, STM_PIN_DATA(2, 10));
Dance 0:de885a6da962 56
Dance 0:de885a6da962 57 // Set ID pin to open drain with pull-up resistor
Dance 0:de885a6da962 58 pin_mode(PA_10, OpenDrain);
Dance 0:de885a6da962 59 GPIOA->PUPDR &= ~(0x3 << 20);
Dance 0:de885a6da962 60 GPIOA->PUPDR |= 1 << 20;
Dance 0:de885a6da962 61
Dance 0:de885a6da962 62 // Set VBUS pin to open drain
Dance 0:de885a6da962 63 pin_mode(PA_9, OpenDrain);
Dance 0:de885a6da962 64
Dance 0:de885a6da962 65 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
Dance 0:de885a6da962 66
Dance 0:de885a6da962 67 // Enable interrupts
Dance 0:de885a6da962 68 OTG_FS->GREGS.GAHBCFG |= (1 << 0);
Dance 0:de885a6da962 69
Dance 0:de885a6da962 70 // Turnaround time to maximum value - too small causes packet loss
Dance 0:de885a6da962 71 OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
Dance 0:de885a6da962 72
Dance 0:de885a6da962 73 // Unmask global interrupts
Dance 0:de885a6da962 74 OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
Dance 0:de885a6da962 75 (1 << 4) | // RX FIFO not empty
Dance 0:de885a6da962 76 (1 << 12); // USB reset
Dance 0:de885a6da962 77
Dance 0:de885a6da962 78 OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
Dance 0:de885a6da962 79 (1 << 2); // Non-zero-length status OUT handshake
Dance 0:de885a6da962 80
Dance 0:de885a6da962 81 OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
Dance 0:de885a6da962 82 (1 << 16); // Power Up
Dance 0:de885a6da962 83
Dance 0:de885a6da962 84 instance = this;
Dance 0:de885a6da962 85 NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
Dance 0:de885a6da962 86 NVIC_SetPriority(OTG_FS_IRQn, 1);
Dance 0:de885a6da962 87 }
Dance 0:de885a6da962 88
Dance 0:de885a6da962 89 USBHAL::~USBHAL(void) {
Dance 0:de885a6da962 90 }
Dance 0:de885a6da962 91
Dance 0:de885a6da962 92 void USBHAL::connect(void) {
Dance 0:de885a6da962 93 NVIC_EnableIRQ(OTG_FS_IRQn);
Dance 0:de885a6da962 94 }
Dance 0:de885a6da962 95
Dance 0:de885a6da962 96 void USBHAL::disconnect(void) {
Dance 0:de885a6da962 97 NVIC_DisableIRQ(OTG_FS_IRQn);
Dance 0:de885a6da962 98 }
Dance 0:de885a6da962 99
Dance 0:de885a6da962 100 void USBHAL::configureDevice(void) {
Dance 0:de885a6da962 101 // Not needed
Dance 0:de885a6da962 102 }
Dance 0:de885a6da962 103
Dance 0:de885a6da962 104 void USBHAL::unconfigureDevice(void) {
Dance 0:de885a6da962 105 // Not needed
Dance 0:de885a6da962 106 }
Dance 0:de885a6da962 107
Dance 0:de885a6da962 108 void USBHAL::setAddress(uint8_t address) {
Dance 0:de885a6da962 109 OTG_FS->DREGS.DCFG |= (address << 4);
Dance 0:de885a6da962 110 EP0write(0, 0);
Dance 0:de885a6da962 111 }
Dance 0:de885a6da962 112
Dance 0:de885a6da962 113 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
Dance 0:de885a6da962 114 uint32_t flags) {
Dance 0:de885a6da962 115 uint32_t epIndex = endpoint >> 1;
Dance 0:de885a6da962 116
Dance 0:de885a6da962 117 uint32_t type;
Dance 0:de885a6da962 118 switch (endpoint) {
Dance 0:de885a6da962 119 case EP0IN:
Dance 0:de885a6da962 120 case EP0OUT:
Dance 0:de885a6da962 121 type = 0;
Dance 0:de885a6da962 122 break;
Dance 0:de885a6da962 123 case EPISO_IN:
Dance 0:de885a6da962 124 case EPISO_OUT:
Dance 0:de885a6da962 125 type = 1;
Dance 0:de885a6da962 126 case EPBULK_IN:
Dance 0:de885a6da962 127 case EPBULK_OUT:
Dance 0:de885a6da962 128 type = 2;
Dance 0:de885a6da962 129 break;
Dance 0:de885a6da962 130 case EPINT_IN:
Dance 0:de885a6da962 131 case EPINT_OUT:
Dance 0:de885a6da962 132 type = 3;
Dance 0:de885a6da962 133 break;
Dance 0:de885a6da962 134 }
Dance 0:de885a6da962 135
Dance 0:de885a6da962 136 // Generic in or out EP controls
Dance 0:de885a6da962 137 uint32_t control = (maxPacket << 0) | // Packet size
Dance 0:de885a6da962 138 (1 << 15) | // Active endpoint
Dance 0:de885a6da962 139 (type << 18); // Endpoint type
Dance 0:de885a6da962 140
Dance 0:de885a6da962 141 if (endpoint & 0x1) { // In Endpoint
Dance 0:de885a6da962 142 // Set up the Tx FIFO
Dance 0:de885a6da962 143 if (endpoint == EP0IN) {
Dance 0:de885a6da962 144 OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
Dance 0:de885a6da962 145 (bufferEnd << 0);
Dance 0:de885a6da962 146 }
Dance 0:de885a6da962 147 else {
Dance 0:de885a6da962 148 OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
Dance 0:de885a6da962 149 (bufferEnd << 0);
Dance 0:de885a6da962 150 }
Dance 0:de885a6da962 151 bufferEnd += maxPacket >> 2;
Dance 0:de885a6da962 152
Dance 0:de885a6da962 153 // Set the In EP specific control settings
Dance 0:de885a6da962 154 if (endpoint != EP0IN) {
Dance 0:de885a6da962 155 control |= (1 << 28); // SD0PID
Dance 0:de885a6da962 156 }
Dance 0:de885a6da962 157
Dance 0:de885a6da962 158 control |= (epIndex << 22) | // TxFIFO index
Dance 0:de885a6da962 159 (1 << 27); // SNAK
Dance 0:de885a6da962 160 OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
Dance 0:de885a6da962 161
Dance 0:de885a6da962 162 // Unmask the interrupt
Dance 0:de885a6da962 163 OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
Dance 0:de885a6da962 164 }
Dance 0:de885a6da962 165 else { // Out endpoint
Dance 0:de885a6da962 166 // Set the out EP specific control settings
Dance 0:de885a6da962 167 control |= (1 << 26); // CNAK
Dance 0:de885a6da962 168 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
Dance 0:de885a6da962 169
Dance 0:de885a6da962 170 // Unmask the interrupt
Dance 0:de885a6da962 171 OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
Dance 0:de885a6da962 172 }
Dance 0:de885a6da962 173 return true;
Dance 0:de885a6da962 174 }
Dance 0:de885a6da962 175
Dance 0:de885a6da962 176 // read setup packet
Dance 0:de885a6da962 177 void USBHAL::EP0setup(uint8_t *buffer) {
Dance 0:de885a6da962 178 memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
Dance 0:de885a6da962 179 }
Dance 0:de885a6da962 180
Dance 0:de885a6da962 181 void USBHAL::EP0readStage(void) {
Dance 0:de885a6da962 182 }
Dance 0:de885a6da962 183
Dance 0:de885a6da962 184 void USBHAL::EP0read(void) {
Dance 0:de885a6da962 185 }
Dance 0:de885a6da962 186
Dance 0:de885a6da962 187 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
Dance 0:de885a6da962 188 uint32_t* buffer32 = (uint32_t *) buffer;
Dance 0:de885a6da962 189 uint32_t length = rxFifoCount;
Dance 0:de885a6da962 190 for (uint32_t i = 0; i < length; i += 4) {
Dance 0:de885a6da962 191 buffer32[i >> 2] = OTG_FS->FIFO[0][0];
Dance 0:de885a6da962 192 }
Dance 0:de885a6da962 193
Dance 0:de885a6da962 194 rxFifoCount = 0;
Dance 0:de885a6da962 195 return length;
Dance 0:de885a6da962 196 }
Dance 0:de885a6da962 197
Dance 0:de885a6da962 198 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
Dance 0:de885a6da962 199 endpointWrite(0, buffer, size);
Dance 0:de885a6da962 200 }
Dance 0:de885a6da962 201
Dance 0:de885a6da962 202 void USBHAL::EP0getWriteResult(void) {
Dance 0:de885a6da962 203 }
Dance 0:de885a6da962 204
Dance 0:de885a6da962 205 void USBHAL::EP0stall(void) {
Dance 0:de885a6da962 206 // If we stall the out endpoint here then we have problems transferring
Dance 0:de885a6da962 207 // and setup requests after the (stalled) get device qualifier requests.
Dance 0:de885a6da962 208 // TODO: Find out if this is correct behavior, or whether we are doing
Dance 0:de885a6da962 209 // something else wrong
Dance 0:de885a6da962 210 stallEndpoint(EP0IN);
Dance 0:de885a6da962 211 // stallEndpoint(EP0OUT);
Dance 0:de885a6da962 212 }
Dance 0:de885a6da962 213
Dance 0:de885a6da962 214 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
Dance 0:de885a6da962 215 uint32_t epIndex = endpoint >> 1;
Dance 0:de885a6da962 216 uint32_t size = (1 << 19) | // 1 packet
Dance 0:de885a6da962 217 (maximumSize << 0); // Packet size
Dance 0:de885a6da962 218 // if (endpoint == EP0OUT) {
Dance 0:de885a6da962 219 size |= (1 << 29); // 1 setup packet
Dance 0:de885a6da962 220 // }
Dance 0:de885a6da962 221 OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
Dance 0:de885a6da962 222 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
Dance 0:de885a6da962 223 (1 << 26); // Clear NAK
Dance 0:de885a6da962 224
Dance 0:de885a6da962 225 epComplete &= ~(1 << endpoint);
Dance 0:de885a6da962 226 return EP_PENDING;
Dance 0:de885a6da962 227 }
Dance 0:de885a6da962 228
Dance 0:de885a6da962 229 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
Dance 0:de885a6da962 230 if (!(epComplete & (1 << endpoint))) {
Dance 0:de885a6da962 231 return EP_PENDING;
Dance 0:de885a6da962 232 }
Dance 0:de885a6da962 233
Dance 0:de885a6da962 234 uint32_t* buffer32 = (uint32_t *) buffer;
Dance 0:de885a6da962 235 uint32_t length = rxFifoCount;
Dance 0:de885a6da962 236 for (uint32_t i = 0; i < length; i += 4) {
Dance 0:de885a6da962 237 buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
Dance 0:de885a6da962 238 }
Dance 0:de885a6da962 239 rxFifoCount = 0;
Dance 0:de885a6da962 240 *bytesRead = length;
Dance 0:de885a6da962 241 return EP_COMPLETED;
Dance 0:de885a6da962 242 }
Dance 0:de885a6da962 243
Dance 0:de885a6da962 244 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
Dance 0:de885a6da962 245 uint32_t epIndex = endpoint >> 1;
Dance 0:de885a6da962 246 OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
Dance 0:de885a6da962 247 (size << 0); // Size of packet
Dance 0:de885a6da962 248 OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
Dance 0:de885a6da962 249 (1 << 26); // CNAK
Dance 0:de885a6da962 250 OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
Dance 0:de885a6da962 251
Dance 0:de885a6da962 252 while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
Dance 0:de885a6da962 253
Dance 0:de885a6da962 254 for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
Dance 0:de885a6da962 255 OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
Dance 0:de885a6da962 256 }
Dance 0:de885a6da962 257
Dance 0:de885a6da962 258 epComplete &= ~(1 << endpoint);
Dance 0:de885a6da962 259
Dance 0:de885a6da962 260 return EP_PENDING;
Dance 0:de885a6da962 261 }
Dance 0:de885a6da962 262
Dance 0:de885a6da962 263 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
Dance 0:de885a6da962 264 if (epComplete & (1 << endpoint)) {
Dance 0:de885a6da962 265 epComplete &= ~(1 << endpoint);
Dance 0:de885a6da962 266 return EP_COMPLETED;
Dance 0:de885a6da962 267 }
Dance 0:de885a6da962 268
Dance 0:de885a6da962 269 return EP_PENDING;
Dance 0:de885a6da962 270 }
Dance 0:de885a6da962 271
Dance 0:de885a6da962 272 void USBHAL::stallEndpoint(uint8_t endpoint) {
Dance 0:de885a6da962 273 if (endpoint & 0x1) { // In EP
Dance 0:de885a6da962 274 OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
Dance 0:de885a6da962 275 (1 << 21); // Stall
Dance 0:de885a6da962 276 }
Dance 0:de885a6da962 277 else { // Out EP
Dance 0:de885a6da962 278 OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
Dance 0:de885a6da962 279 OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
Dance 0:de885a6da962 280 (1 << 21); // Stall
Dance 0:de885a6da962 281 }
Dance 0:de885a6da962 282 }
Dance 0:de885a6da962 283
Dance 0:de885a6da962 284 void USBHAL::unstallEndpoint(uint8_t endpoint) {
Dance 0:de885a6da962 285
Dance 0:de885a6da962 286 }
Dance 0:de885a6da962 287
Dance 0:de885a6da962 288 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
Dance 0:de885a6da962 289 return false;
Dance 0:de885a6da962 290 }
Dance 0:de885a6da962 291
Dance 0:de885a6da962 292 void USBHAL::remoteWakeup(void) {
Dance 0:de885a6da962 293 }
Dance 0:de885a6da962 294
Dance 0:de885a6da962 295
Dance 0:de885a6da962 296 void USBHAL::_usbisr(void) {
Dance 0:de885a6da962 297 instance->usbisr();
Dance 0:de885a6da962 298 }
Dance 0:de885a6da962 299
Dance 0:de885a6da962 300
Dance 0:de885a6da962 301 void USBHAL::usbisr(void) {
Dance 0:de885a6da962 302 if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
Dance 0:de885a6da962 303 // Set SNAK bits
Dance 0:de885a6da962 304 OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
Dance 0:de885a6da962 305 OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
Dance 0:de885a6da962 306 OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
Dance 0:de885a6da962 307 OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
Dance 0:de885a6da962 308
Dance 0:de885a6da962 309 OTG_FS->DREGS.DIEPMSK = (1 << 0);
Dance 0:de885a6da962 310
Dance 0:de885a6da962 311 bufferEnd = 0;
Dance 0:de885a6da962 312
Dance 0:de885a6da962 313 // Set the receive FIFO size
Dance 0:de885a6da962 314 OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
Dance 0:de885a6da962 315 bufferEnd += rxFifoSize >> 2;
Dance 0:de885a6da962 316
Dance 0:de885a6da962 317 // Create the endpoints, and wait for setup packets on out EP0
Dance 0:de885a6da962 318 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
Dance 0:de885a6da962 319 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
Dance 0:de885a6da962 320 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
Dance 0:de885a6da962 321
Dance 0:de885a6da962 322 OTG_FS->GREGS.GINTSTS = (1 << 12);
Dance 0:de885a6da962 323 }
Dance 0:de885a6da962 324
Dance 0:de885a6da962 325 if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
Dance 0:de885a6da962 326 uint32_t status = OTG_FS->GREGS.GRXSTSP;
Dance 0:de885a6da962 327
Dance 0:de885a6da962 328 uint32_t endpoint = (status & 0xF) << 1;
Dance 0:de885a6da962 329 uint32_t length = (status >> 4) & 0x7FF;
Dance 0:de885a6da962 330 uint32_t type = (status >> 17) & 0xF;
Dance 0:de885a6da962 331
Dance 0:de885a6da962 332 rxFifoCount = length;
Dance 0:de885a6da962 333
Dance 0:de885a6da962 334 if (type == 0x6) {
Dance 0:de885a6da962 335 // Setup packet
Dance 0:de885a6da962 336 for (uint32_t i=0; i<length; i+=4) {
Dance 0:de885a6da962 337 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
Dance 0:de885a6da962 338 }
Dance 0:de885a6da962 339 rxFifoCount = 0;
Dance 0:de885a6da962 340 }
Dance 0:de885a6da962 341
Dance 0:de885a6da962 342 if (type == 0x4) {
Dance 0:de885a6da962 343 // Setup complete
Dance 0:de885a6da962 344 EP0setupCallback();
Dance 0:de885a6da962 345 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
Dance 0:de885a6da962 346 }
Dance 0:de885a6da962 347
Dance 0:de885a6da962 348 if (type == 0x2) {
Dance 0:de885a6da962 349 // Out packet
Dance 0:de885a6da962 350 if (endpoint == EP0OUT) {
Dance 0:de885a6da962 351 EP0out();
Dance 0:de885a6da962 352 }
Dance 0:de885a6da962 353 else {
Dance 0:de885a6da962 354 epComplete |= (1 << endpoint);
Dance 0:de885a6da962 355 if ((instance->*(epCallback[endpoint - 2]))()) {
Dance 0:de885a6da962 356 epComplete &= (1 << endpoint);
Dance 0:de885a6da962 357 }
Dance 0:de885a6da962 358 }
Dance 0:de885a6da962 359 }
Dance 0:de885a6da962 360
Dance 0:de885a6da962 361 for (uint32_t i=0; i<rxFifoCount; i+=4) {
Dance 0:de885a6da962 362 (void) OTG_FS->FIFO[0][0];
Dance 0:de885a6da962 363 }
Dance 0:de885a6da962 364 OTG_FS->GREGS.GINTSTS = (1 << 4);
Dance 0:de885a6da962 365 }
Dance 0:de885a6da962 366
Dance 0:de885a6da962 367 if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
Dance 0:de885a6da962 368 // Loop through the in endpoints
Dance 0:de885a6da962 369 for (uint32_t i=0; i<4; i++) {
Dance 0:de885a6da962 370 if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
Dance 0:de885a6da962 371
Dance 0:de885a6da962 372 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
Dance 0:de885a6da962 373 // If the Tx FIFO is empty on EP0 we need to send a further
Dance 0:de885a6da962 374 // packet, so call EP0in()
Dance 0:de885a6da962 375 if (i == 0) {
Dance 0:de885a6da962 376 EP0in();
Dance 0:de885a6da962 377 }
Dance 0:de885a6da962 378 // Clear the interrupt
Dance 0:de885a6da962 379 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
Dance 0:de885a6da962 380 // Stop firing Tx empty interrupts
Dance 0:de885a6da962 381 // Will get turned on again if another write is called
Dance 0:de885a6da962 382 OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
Dance 0:de885a6da962 383 }
Dance 0:de885a6da962 384
Dance 0:de885a6da962 385 // If the transfer is complete
Dance 0:de885a6da962 386 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
Dance 0:de885a6da962 387 epComplete |= (1 << (1 + (i << 1)));
Dance 0:de885a6da962 388 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
Dance 0:de885a6da962 389 }
Dance 0:de885a6da962 390 }
Dance 0:de885a6da962 391 }
Dance 0:de885a6da962 392 OTG_FS->GREGS.GINTSTS = (1 << 18);
Dance 0:de885a6da962 393 }
Dance 0:de885a6da962 394
Dance 0:de885a6da962 395 if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
Dance 0:de885a6da962 396 SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
Dance 0:de885a6da962 397 OTG_FS->GREGS.GINTSTS = (1 << 3);
Dance 0:de885a6da962 398 }
Dance 0:de885a6da962 399 }
Dance 0:de885a6da962 400
Dance 0:de885a6da962 401
Dance 0:de885a6da962 402 #endif