CQ Publishing / MARMEX_VB

MARMEX-VB : "Mary Camera module" library

Dependents:   MARMEX_VB_test MARMEX_VB_Hello

MARMEX-VB (MARY-VB) camera module library for mbed. (This module may be available in Japan only.)

Kown problem / 既知の問題

The read data may have contouring. In this case, it may require reset or changing order of data reading. The order change API is available as "read_order_change()" function.
カメラから読み出したデータに擬似輪郭が発生することがあります．この問題にはシステム全体のリセットを行うか，または読み出し順の変更を行うことで対処して下さい．読み出し順の変更はAPIの"read_order_change()"関数を使うことができます．

MARMEX_VB.cpp@5:84e6c89a9a6d, 2014-06-20 (annotated)

Committer:
nxpfan
Date:
Fri Jun 20 09:05:19 2014 +0000
Revision:
5:84e6c89a9a6d
Parent:
4:8ef31b67c0ab 
SPI-FIFO operation option added

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nxpfan 0:c4d14dd5d479 1 /** MARMEX_VB Camera control library
nxpfan 0:c4d14dd5d479 2 *
nxpfan 0:c4d14dd5d479 3 * @class MARMEX_VB
nxpfan 5:84e6c89a9a6d 4 * @version 0.5
nxpfan 5:84e6c89a9a6d 5 * @date 20-Jun-2014
nxpfan 0:c4d14dd5d479 6 *
nxpfan 0:c4d14dd5d479 7 * Released under the Apache License, Version 2.0 : http://mbed.org/handbook/Apache-Licence
nxpfan 0:c4d14dd5d479 8 *
nxpfan 0:c4d14dd5d479 9 * MARMEX_VB Camera control library for mbed
nxpfan 0:c4d14dd5d479 10 */
nxpfan 0:c4d14dd5d479 11
nxpfan 0:c4d14dd5d479 12 #include "mbed.h"
nxpfan 0:c4d14dd5d479 13 #include "MARMEX_VB.h"
nxpfan 0:c4d14dd5d479 14
nxpfan 0:c4d14dd5d479 15 #define SPI_FREQUENCY (12 * 1000 * 1000)
nxpfan 0:c4d14dd5d479 16
nxpfan 5:84e6c89a9a6d 17 /*
nxpfan 5:84e6c89a9a6d 18 * Followings are 3 types of line read routines.
nxpfan 5:84e6c89a9a6d 19 * Choose one of next 3 methods for reading camera data trough SPI interface
nxpfan 5:84e6c89a9a6d 20 *
nxpfan 5:84e6c89a9a6d 21 * Type0: "LINE_READ_OPT" is define as "NO_OPTIMIZATION"
nxpfan 5:84e6c89a9a6d 22 * Most basic loop to explain how the MCU reading the line data.
nxpfan 5:84e6c89a9a6d 23 * But this routine is slow, because the loop does 1 byte read
nxpfan 5:84e6c89a9a6d 24 * with ChipSelect signal assertion/deassertion by DigitalOut
nxpfan 5:84e6c89a9a6d 25 *
nxpfan 5:84e6c89a9a6d 26 * Type1: "LINE_READ_OPT" is define as "LOOP_UNROLL"
nxpfan 5:84e6c89a9a6d 27 * Faster. And keeping compatibility on mbed-SDK.
nxpfan 5:84e6c89a9a6d 28 * Data reading speed improvement has been done in two ways.
nxpfan 5:84e6c89a9a6d 29 * * The ChipSelect signal is kept asserted for whole line data transfer.
nxpfan 5:84e6c89a9a6d 30 * because the MARMEX-VB module does not need deassertion at each end of byte transfer.
nxpfan 5:84e6c89a9a6d 31 * * Loop unrolled. minimized loop overhead
nxpfan 5:84e6c89a9a6d 32 *
nxpfan 5:84e6c89a9a6d 33 * Type2: "LINE_READ_OPT" is define as "USING_SSP_FIFO"
nxpfan 5:84e6c89a9a6d 34 * Fastest but no compatibility with mbed-SDK.
nxpfan 5:84e6c89a9a6d 35 * The optimization has been done to use FIFO of SSP block.
nxpfan 5:84e6c89a9a6d 36 * This code makes data transfer efficiency maximum.
nxpfan 5:84e6c89a9a6d 37 * However, since this optimization is done in very low level (by register accessing),
nxpfan 5:84e6c89a9a6d 38 * it works on some MCU's only (test has been done on LPC1768, LPC11U24 and LPC11U35).
nxpfan 5:84e6c89a9a6d 39 *
nxpfan 5:84e6c89a9a6d 40 * And user need to care about which SSP block is used. For instance, if the SPI pins
nxpfan 5:84e6c89a9a6d 41 * of p5, p6 and p7 are used, those are connected to SSP1 in LPC1768. In case of
nxpfan 5:84e6c89a9a6d 42 * LPC11U24 and LPC11U35, those pins are routed to SSP0.
nxpfan 5:84e6c89a9a6d 43 * These settings should be done manually
nxpfan 5:84e6c89a9a6d 44 */
nxpfan 5:84e6c89a9a6d 45
nxpfan 5:84e6c89a9a6d 46 //#define LINE_READ_OPT NO_OPTIMIZATION
nxpfan 5:84e6c89a9a6d 47 #define LINE_READ_OPT LOOP_UNROLL
nxpfan 5:84e6c89a9a6d 48 //#define LINE_READ_OPT USING_SSP_FIFO
nxpfan 5:84e6c89a9a6d 49
nxpfan 5:84e6c89a9a6d 50
nxpfan 5:84e6c89a9a6d 51 /* Setting for "LINE_READ_OPT == USING_SSP_FIFO"
nxpfan 5:84e6c89a9a6d 52 * Choose one line from next 3 lines when the FIFO option is taken
nxpfan 5:84e6c89a9a6d 53 */
nxpfan 5:84e6c89a9a6d 54
nxpfan 5:84e6c89a9a6d 55 #define SSP_AUTO_SELECTION // for demo setup on "MAPLE mini type-B (MARM03-BASE)" baseboard (slot2) with a MARMEX_OB module (on slot1)
nxpfan 5:84e6c89a9a6d 56 //#define SSP_USE_SSP0
nxpfan 5:84e6c89a9a6d 57 //#define SSP_USE_SSP1
nxpfan 5:84e6c89a9a6d 58
nxpfan 5:84e6c89a9a6d 59
nxpfan 5:84e6c89a9a6d 60
nxpfan 5:84e6c89a9a6d 61
nxpfan 0:c4d14dd5d479 62 MARMEX_VB::MARMEX_VB(
nxpfan 0:c4d14dd5d479 63 PinName SPI_mosi,
nxpfan 0:c4d14dd5d479 64 PinName SPI_miso,
nxpfan 0:c4d14dd5d479 65 PinName SPI_sck,
nxpfan 0:c4d14dd5d479 66 PinName SPI_cs,
nxpfan 0:c4d14dd5d479 67 PinName cam_reset,
nxpfan 0:c4d14dd5d479 68 PinName I2C_sda,
nxpfan 0:c4d14dd5d479 69 PinName I2C_scl
nxpfan 0:c4d14dd5d479 70 ) :
nxpfan 0:c4d14dd5d479 71 _spi( SPI_mosi, SPI_miso, SPI_sck ),
nxpfan 0:c4d14dd5d479 72 _cs( SPI_cs ),
nxpfan 0:c4d14dd5d479 73 _reset( cam_reset ),
nxpfan 0:c4d14dd5d479 74 _i2c( I2C_sda, I2C_scl )
nxpfan 0:c4d14dd5d479 75 {
nxpfan 0:c4d14dd5d479 76 #ifdef IGNORE_INITIALIZATION_ERROR
nxpfan 0:c4d14dd5d479 77 init();
nxpfan 0:c4d14dd5d479 78 #else
nxpfan 0:c4d14dd5d479 79 if ( 0 != init() )
nxpfan 0:c4d14dd5d479 80 error( "camera initialization failed." );
nxpfan 0:c4d14dd5d479 81 #endif
nxpfan 0:c4d14dd5d479 82 }
nxpfan 0:c4d14dd5d479 83
nxpfan 0:c4d14dd5d479 84
nxpfan 0:c4d14dd5d479 85 #define CAM_I2C_ADDR 0x42
nxpfan 0:c4d14dd5d479 86
nxpfan 0:c4d14dd5d479 87 #define COMMAND_WRITE 0x00
nxpfan 0:c4d14dd5d479 88 #define COMMAND_READ 0x80
nxpfan 0:c4d14dd5d479 89 #define COMMAND_ADDR_INCREMENT 0x20
nxpfan 0:c4d14dd5d479 90
nxpfan 0:c4d14dd5d479 91 #define MEMORY_ADDR_LOW__REGISTER 0x0
nxpfan 0:c4d14dd5d479 92 #define MEMORY_ADDR_MID__REGISTER 0x1
nxpfan 0:c4d14dd5d479 93 #define MEMORY_ADDR_HIGH_REGISTER 0x2
nxpfan 0:c4d14dd5d479 94 #define CAMERA_DATA_REGISTER 0x8
nxpfan 0:c4d14dd5d479 95 #define CONTROL_DATA_REGISTER 0x3
nxpfan 0:c4d14dd5d479 96 #define STATUS_REGISTER 0x4
nxpfan 0:c4d14dd5d479 97
nxpfan 0:c4d14dd5d479 98 #define CONTROL__PAUSE_BUFFER_UPDATE 0x01
nxpfan 0:c4d14dd5d479 99 #define CONTROL__RESUME_BUFFER_UPDATE 0x00
nxpfan 0:c4d14dd5d479 100
nxpfan 0:c4d14dd5d479 101
nxpfan 0:c4d14dd5d479 102 int MARMEX_VB::init( CameraResolution res )
nxpfan 0:c4d14dd5d479 103 {
nxpfan 0:c4d14dd5d479 104 #define PARAM_NUM 99
nxpfan 0:c4d14dd5d479 105 #define RES_CHANGE_PARAM_NUM 12
nxpfan 0:c4d14dd5d479 106 #define RESET_PULSE_WIDTH 100 // mili-seconds
nxpfan 0:c4d14dd5d479 107 #define RESET_RECOVERY_TIME 100 // mili-seconds
nxpfan 0:c4d14dd5d479 108 #define COMMAND_INTERVAL 20 // mili-seconds
nxpfan 0:c4d14dd5d479 109
nxpfan 0:c4d14dd5d479 110 char camera_register_setting[ PARAM_NUM ][ 2 ] = {
nxpfan 0:c4d14dd5d479 111 { 0x01, 0x40 }, { 0x02, 0x60 }, { 0x03, 0x02 }, { 0x0C, 0x0C },
nxpfan 0:c4d14dd5d479 112 { 0x0E, 0x61 }, { 0x0F, 0x4B }, { 0x11, 0x80 }, { 0x12, 0x04 },
nxpfan 0:c4d14dd5d479 113 { 0x15, 0x00 }, { 0x16, 0x02 }, { 0x17, 0x39 }, { 0x18, 0x03 },
nxpfan 0:c4d14dd5d479 114 { 0x19, 0x03 }, { 0x1A, 0x7B }, { 0x1E, 0x37 }, { 0x21, 0x02 },
nxpfan 0:c4d14dd5d479 115 { 0x22, 0x91 }, { 0x29, 0x07 }, { 0x32, 0x80 }, { 0x33, 0x0B },
nxpfan 0:c4d14dd5d479 116 { 0x34, 0x11 }, { 0x35, 0x0B }, { 0x37, 0x1D }, { 0x38, 0x71 },
nxpfan 0:c4d14dd5d479 117 { 0x39, 0x2A }, { 0x3B, 0x12 }, { 0x3C, 0x78 }, { 0x3D, 0xC3 },
nxpfan 0:c4d14dd5d479 118 { 0x3E, 0x11 }, { 0x3F, 0x00 }, { 0x40, 0xD0 }, { 0x41, 0x08 },
nxpfan 0:c4d14dd5d479 119 { 0x41, 0x38 }, { 0x43, 0x0A }, { 0x44, 0xF0 }, { 0x45, 0x34 },
nxpfan 0:c4d14dd5d479 120 { 0x46, 0x58 }, { 0x47, 0x28 }, { 0x48, 0x3A }, { 0x4B, 0x09 },
nxpfan 0:c4d14dd5d479 121 { 0x4C, 0x00 }, { 0x4D, 0x40 }, { 0x4E, 0x20 }, { 0x4F, 0x80 },
nxpfan 0:c4d14dd5d479 122 { 0x50, 0x80 }, { 0x51, 0x00 }, { 0x52, 0x22 }, { 0x53, 0x5E },
nxpfan 0:c4d14dd5d479 123 { 0x54, 0x80 }, { 0x56, 0x40 }, { 0x58, 0x9E }, { 0x59, 0x88 },
nxpfan 0:c4d14dd5d479 124 { 0x5A, 0x88 }, { 0x5B, 0x44 }, { 0x5C, 0x67 }, { 0x5D, 0x49 },
nxpfan 0:c4d14dd5d479 125 { 0x5E, 0x0E }, { 0x69, 0x00 }, { 0x6A, 0x40 }, { 0x6B, 0x0A },
nxpfan 0:c4d14dd5d479 126 { 0x6C, 0x0A }, { 0x6D, 0x55 }, { 0x6E, 0x11 }, { 0x6F, 0x9F },
nxpfan 0:c4d14dd5d479 127 { 0x70, 0x3A }, { 0x71, 0x35 }, { 0x72, 0x11 }, { 0x73, 0xF1 },
nxpfan 0:c4d14dd5d479 128 { 0x74, 0x10 }, { 0x75, 0x05 }, { 0x76, 0xE1 }, { 0x77, 0x01 },
nxpfan 0:c4d14dd5d479 129 { 0x78, 0x04 }, { 0x79, 0x01 }, { 0x8D, 0x4F }, { 0x8E, 0x00 },
nxpfan 0:c4d14dd5d479 130 { 0x8F, 0x00 }, { 0x90, 0x00 }, { 0x91, 0x00 }, { 0x96, 0x00 },
nxpfan 0:c4d14dd5d479 131 { 0x96, 0x00 }, { 0x97, 0x30 }, { 0x98, 0x20 }, { 0x99, 0x30 },
nxpfan 0:c4d14dd5d479 132 { 0x9A, 0x00 }, { 0x9A, 0x84 }, { 0x9B, 0x29 }, { 0x9C, 0x03 },
nxpfan 0:c4d14dd5d479 133 { 0x9D, 0x4C }, { 0x9E, 0x3F }, { 0xA2, 0x52 }, { 0xA4, 0x88 },
nxpfan 0:c4d14dd5d479 134 { 0xB0, 0x84 }, { 0xB1, 0x0C }, { 0xB2, 0x0E }, { 0xB3, 0x82 },
nxpfan 0:c4d14dd5d479 135 { 0xB8, 0x0A }, { 0xC8, 0xF0 }, { 0xC9, 0x60 },
nxpfan 0:c4d14dd5d479 136 };
nxpfan 0:c4d14dd5d479 137 const char res_change_param[ 5 ][ RES_CHANGE_PARAM_NUM ] = {
nxpfan 0:c4d14dd5d479 138 { 0x17, 0x18, 0x32, 0x19, 0x1a, 0x03, 0x0c, 0x3e, 0x71, 0x72, 0x73, 0xa2 }, // register addr
nxpfan 0:c4d14dd5d479 139 { 0x39, 0x03, 0x80, 0x03, 0x7b, 0x02, 0x0c, 0x11, 0x35, 0x11, 0xf1, 0x52 }, // QSIF
nxpfan 0:c4d14dd5d479 140 { 0x13, 0x01, 0xb6, 0x02, 0x7a, 0x0a, 0x00, 0x00, 0x35, 0x11, 0xf0, 0x02 }, // VGA
nxpfan 0:c4d14dd5d479 141 { 0x16, 0x04, 0x80, 0x02, 0x7a, 0x0a, 0x04, 0x19, 0x35, 0x11, 0xf1, 0x02 }, // QVGA
nxpfan 0:c4d14dd5d479 142 { 0x16, 0x04, 0xa4, 0x02, 0x7a, 0x0a, 0x04, 0x1a, 0x35, 0x22, 0xf2, 0x02 }, // QQVGA
nxpfan 0:c4d14dd5d479 143 };
nxpfan 0:c4d14dd5d479 144 const char camera_reset_command[] = { 0x12, 0x80 };
nxpfan 0:c4d14dd5d479 145
nxpfan 0:c4d14dd5d479 146 _read_order_change = 0;
nxpfan 0:c4d14dd5d479 147
nxpfan 0:c4d14dd5d479 148 // SPI settings
nxpfan 0:c4d14dd5d479 149
nxpfan 1:b2324313d4da 150
nxpfan 0:c4d14dd5d479 151 _cs = 1; // set ChipSelect signal HIGH
nxpfan 0:c4d14dd5d479 152 _spi.format( 8 ); // camera SPI : 8bits/transfer
nxpfan 0:c4d14dd5d479 153 _spi.frequency( SPI_FREQUENCY ); // SPI frequency setting
nxpfan 0:c4d14dd5d479 154 _i2c.frequency( 400 * 1000 );
nxpfan 0:c4d14dd5d479 155
nxpfan 0:c4d14dd5d479 156 // reset
nxpfan 0:c4d14dd5d479 157
nxpfan 0:c4d14dd5d479 158 _reset = 0;
nxpfan 0:c4d14dd5d479 159 wait_ms( RESET_PULSE_WIDTH ); // assert RESET signal
nxpfan 0:c4d14dd5d479 160 _reset = 1;
nxpfan 0:c4d14dd5d479 161 wait_ms( RESET_RECOVERY_TIME ); // deassert RESET signal
nxpfan 0:c4d14dd5d479 162
nxpfan 0:c4d14dd5d479 163 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, camera_reset_command, 2 )) )
nxpfan 0:c4d14dd5d479 164 return _error_state; // return non-zero if I2C access failed
nxpfan 0:c4d14dd5d479 165
nxpfan 0:c4d14dd5d479 166 wait_ms( 100 ); // reset (via I2C) recovery time
nxpfan 0:c4d14dd5d479 167
nxpfan 0:c4d14dd5d479 168 _horizontal_size = QCIF_PIXEL_PER_LINE;
nxpfan 0:c4d14dd5d479 169 _vertical_size = QCIF_LINE_PER_FRAME;
nxpfan 0:c4d14dd5d479 170
nxpfan 0:c4d14dd5d479 171 #ifdef UNIFIED_RESOLUTION_CHANGE
nxpfan 0:c4d14dd5d479 172 if ( QCIF != res ) {
nxpfan 0:c4d14dd5d479 173 for ( int i = 0; i < RES_CHANGE_PARAM_NUM; i++ ) {
nxpfan 0:c4d14dd5d479 174 for ( int j = 0; j < PARAM_NUM; j++ ) {
nxpfan 0:c4d14dd5d479 175 if ( camera_register_setting[ j ][ 0 ] == res_change_param[ 0 ][ i ] ) {
nxpfan 0:c4d14dd5d479 176 camera_register_setting[ j ][ 1 ] = res_change_param[ res ][ i ];
nxpfan 0:c4d14dd5d479 177 }
nxpfan 0:c4d14dd5d479 178 }
nxpfan 0:c4d14dd5d479 179 }
nxpfan 0:c4d14dd5d479 180 }
nxpfan 0:c4d14dd5d479 181
nxpfan 0:c4d14dd5d479 182 switch ( res ) {
nxpfan 0:c4d14dd5d479 183 case QCIF:
nxpfan 0:c4d14dd5d479 184 _horizontal_size = QCIF_PIXEL_PER_LINE;
nxpfan 0:c4d14dd5d479 185 _vertical_size = QCIF_LINE_PER_FRAME;
nxpfan 0:c4d14dd5d479 186 break;
nxpfan 0:c4d14dd5d479 187 case VGA:
nxpfan 0:c4d14dd5d479 188 _horizontal_size = VGA_PIXEL_PER_LINE;
nxpfan 0:c4d14dd5d479 189 _vertical_size = VGA_LINE_PER_FRAME;
nxpfan 0:c4d14dd5d479 190 break;
nxpfan 0:c4d14dd5d479 191 case QVGA:
nxpfan 0:c4d14dd5d479 192 _horizontal_size = VGA_PIXEL_PER_LINE / 2;
nxpfan 0:c4d14dd5d479 193 _vertical_size = VGA_LINE_PER_FRAME / 2;
nxpfan 0:c4d14dd5d479 194 break;
nxpfan 0:c4d14dd5d479 195 case QQVGA:
nxpfan 0:c4d14dd5d479 196 _horizontal_size = VGA_PIXEL_PER_LINE / 4;
nxpfan 0:c4d14dd5d479 197 _vertical_size = VGA_LINE_PER_FRAME / 4;
nxpfan 0:c4d14dd5d479 198 break;
nxpfan 0:c4d14dd5d479 199 }
nxpfan 0:c4d14dd5d479 200 #endif
nxpfan 0:c4d14dd5d479 201
nxpfan 0:c4d14dd5d479 202
nxpfan 0:c4d14dd5d479 203 for ( int i = 0; i < PARAM_NUM; i++ ) {
nxpfan 0:c4d14dd5d479 204 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, camera_register_setting[ i ], 2 )) )
nxpfan 0:c4d14dd5d479 205 break;
nxpfan 0:c4d14dd5d479 206
nxpfan 0:c4d14dd5d479 207 wait_ms( COMMAND_INTERVAL ); // camera register writing requires this interval
nxpfan 0:c4d14dd5d479 208 }
nxpfan 0:c4d14dd5d479 209
nxpfan 0:c4d14dd5d479 210 #ifndef UNIFIED_RESOLUTION_CHANGE
nxpfan 0:c4d14dd5d479 211 if ( QCIF != res ) {
nxpfan 0:c4d14dd5d479 212 char d[ 2 ];
nxpfan 0:c4d14dd5d479 213 for ( int i = 0; i < RES_CHANGE_PARAM_NUM; i++ ) {
nxpfan 0:c4d14dd5d479 214 d[ 0 ] = res_change_param[ 0 ][ i ];
nxpfan 0:c4d14dd5d479 215 d[ 1 ] = res_change_param[ res ][ i ];
nxpfan 0:c4d14dd5d479 216
nxpfan 0:c4d14dd5d479 217 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, d, 2 )) )
nxpfan 0:c4d14dd5d479 218 break;
nxpfan 0:c4d14dd5d479 219
nxpfan 0:c4d14dd5d479 220 wait_ms( COMMAND_INTERVAL ); // camera register writing requires this interval
nxpfan 0:c4d14dd5d479 221 }
nxpfan 0:c4d14dd5d479 222 }
nxpfan 0:c4d14dd5d479 223
nxpfan 0:c4d14dd5d479 224 switch ( res ) {
nxpfan 0:c4d14dd5d479 225 case QCIF:
nxpfan 0:c4d14dd5d479 226 _horizontal_size = QCIF_PIXEL_PER_LINE;
nxpfan 0:c4d14dd5d479 227 _vertical_size = QCIF_LINE_PER_FRAME;
nxpfan 0:c4d14dd5d479 228 break;
nxpfan 0:c4d14dd5d479 229 case VGA:
nxpfan 0:c4d14dd5d479 230 _horizontal_size = VGA_PIXEL_PER_LINE;
nxpfan 0:c4d14dd5d479 231 _vertical_size = VGA_LINE_PER_FRAME;
nxpfan 0:c4d14dd5d479 232 break;
nxpfan 0:c4d14dd5d479 233 case QVGA:
nxpfan 0:c4d14dd5d479 234 _horizontal_size = VGA_PIXEL_PER_LINE / 2;
nxpfan 0:c4d14dd5d479 235 _vertical_size = VGA_LINE_PER_FRAME / 2;
nxpfan 0:c4d14dd5d479 236 break;
nxpfan 0:c4d14dd5d479 237 case QQVGA:
nxpfan 0:c4d14dd5d479 238 _horizontal_size = VGA_PIXEL_PER_LINE / 4;
nxpfan 0:c4d14dd5d479 239 _vertical_size = VGA_LINE_PER_FRAME / 4;
nxpfan 0:c4d14dd5d479 240 break;
nxpfan 0:c4d14dd5d479 241 }
nxpfan 0:c4d14dd5d479 242 #endif
nxpfan 0:c4d14dd5d479 243
nxpfan 0:c4d14dd5d479 244 return _error_state; // return non-zero if I2C access failed
nxpfan 0:c4d14dd5d479 245 }
nxpfan 0:c4d14dd5d479 246
nxpfan 0:c4d14dd5d479 247 void MARMEX_VB::colorbar( SwitchState sw )
nxpfan 0:c4d14dd5d479 248 {
nxpfan 0:c4d14dd5d479 249 char s[ 2 ];
nxpfan 0:c4d14dd5d479 250
nxpfan 0:c4d14dd5d479 251 s[ 0 ] = 0x12;
nxpfan 0:c4d14dd5d479 252 s[ 1 ] = sw ? 0x06 : 0x04;
nxpfan 0:c4d14dd5d479 253
nxpfan 0:c4d14dd5d479 254 _error_state = _i2c.write( CAM_I2C_ADDR, s, 2 );
nxpfan 0:c4d14dd5d479 255 }
nxpfan 0:c4d14dd5d479 256
nxpfan 0:c4d14dd5d479 257 int MARMEX_VB::get_horizontal_size( void )
nxpfan 0:c4d14dd5d479 258 {
nxpfan 0:c4d14dd5d479 259 return _horizontal_size; // return last state of I2C access
nxpfan 0:c4d14dd5d479 260 }
nxpfan 0:c4d14dd5d479 261
nxpfan 0:c4d14dd5d479 262 int MARMEX_VB::get_vertical_size( void )
nxpfan 0:c4d14dd5d479 263 {
nxpfan 0:c4d14dd5d479 264 return _vertical_size; // return last state of I2C access
nxpfan 0:c4d14dd5d479 265 }
nxpfan 0:c4d14dd5d479 266
nxpfan 0:c4d14dd5d479 267 int MARMEX_VB::ready( void )
nxpfan 0:c4d14dd5d479 268 {
nxpfan 0:c4d14dd5d479 269 return _error_state; // return last state of I2C access
nxpfan 0:c4d14dd5d479 270 }
nxpfan 0:c4d14dd5d479 271
nxpfan 0:c4d14dd5d479 272 extern int read_order_change;
nxpfan 0:c4d14dd5d479 273
nxpfan 0:c4d14dd5d479 274 void MARMEX_VB::read_a_line( short *p, int line_number, int x_offset, int n_of_pixels )
nxpfan 5:84e6c89a9a6d 275 {
nxpfan 5:84e6c89a9a6d 276 // OPTION REFERENCE NUMBER (DO NOT EDIT)
nxpfan 5:84e6c89a9a6d 277 #define NO_OPTIMIZATION 0
nxpfan 5:84e6c89a9a6d 278 #define LOOP_UNROLL 1
nxpfan 5:84e6c89a9a6d 279 #define USING_SSP_FIFO 2
nxpfan 0:c4d14dd5d479 280
nxpfan 0:c4d14dd5d479 281 if ( line_number < 0 )
nxpfan 0:c4d14dd5d479 282 return;
nxpfan 0:c4d14dd5d479 283
nxpfan 0:c4d14dd5d479 284 // set camera module's buffer address
nxpfan 0:c4d14dd5d479 285 set_address( line_number * get_horizontal_size() * BYTE_PER_PIXEL + x_offset * BYTE_PER_PIXEL );
nxpfan 0:c4d14dd5d479 286
nxpfan 0:c4d14dd5d479 287 // put a read command, first return byte should be ignored
nxpfan 0:c4d14dd5d479 288 read_register( CAMERA_DATA_REGISTER );
nxpfan 0:c4d14dd5d479 289
nxpfan 0:c4d14dd5d479 290
nxpfan 5:84e6c89a9a6d 291 /*
nxpfan 5:84e6c89a9a6d 292 * Type0: "LINE_READ_OPT" is define as "NO_OPTIMIZATION"
nxpfan 5:84e6c89a9a6d 293 * Most basic loop to explain how the MCU reading the line data.
nxpfan 5:84e6c89a9a6d 294 * But this routine is slow, because the loop does 1 byte read
nxpfan 5:84e6c89a9a6d 295 * with ChipSelect signal assertion/deassertion by DigitalOut
nxpfan 5:84e6c89a9a6d 296 */
nxpfan 5:84e6c89a9a6d 297 #if ( LINE_READ_OPT == NO_OPTIMIZATION )
nxpfan 5:84e6c89a9a6d 298
nxpfan 5:84e6c89a9a6d 299 short tmp;
nxpfan 5:84e6c89a9a6d 300
nxpfan 0:c4d14dd5d479 301 if ( _read_order_change ) {
nxpfan 5:84e6c89a9a6d 302 for( int x = 0; x < n_of_pixels; x++ ) {
nxpfan 5:84e6c89a9a6d 303 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
nxpfan 5:84e6c89a9a6d 304 tmp = read_register( CAMERA_DATA_REGISTER ); // read lower byte
nxpfan 5:84e6c89a9a6d 305 *p++ = (read_register( CAMERA_DATA_REGISTER ) << 8) | tmp; // read upper byte
nxpfan 5:84e6c89a9a6d 306 }
nxpfan 5:84e6c89a9a6d 307 } else {
nxpfan 0:c4d14dd5d479 308
nxpfan 0:c4d14dd5d479 309 read_register( CAMERA_DATA_REGISTER );
nxpfan 0:c4d14dd5d479 310
nxpfan 0:c4d14dd5d479 311 for( int x = 0; x < n_of_pixels; x++ ) {
nxpfan 0:c4d14dd5d479 312 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
nxpfan 0:c4d14dd5d479 313 tmp = read_register( CAMERA_DATA_REGISTER ) << 8; // read lower byte
nxpfan 0:c4d14dd5d479 314 *p++ = (read_register( CAMERA_DATA_REGISTER ) << 0) | tmp; // read upper byte
nxpfan 0:c4d14dd5d479 315 }
nxpfan 5:84e6c89a9a6d 316 }
nxpfan 5:84e6c89a9a6d 317 #endif // ( LINE_READ_OPT == NO_OPTIMIZATION )
nxpfan 0:c4d14dd5d479 318
nxpfan 0:c4d14dd5d479 319
nxpfan 5:84e6c89a9a6d 320 /*
nxpfan 5:84e6c89a9a6d 321 * Type1: "LINE_READ_OPT" is define as "LOOP_UNROLL"
nxpfan 5:84e6c89a9a6d 322 * Faster. And keeping compatibility on mbed-SDK.
nxpfan 5:84e6c89a9a6d 323 * Data reading speed improvement has been done in two ways.
nxpfan 5:84e6c89a9a6d 324 * * The ChipSelect signal is kept asserted for whole line data transfer.
nxpfan 5:84e6c89a9a6d 325 * because the MARMEX-VB module does not need deassertion at each end of byte transfer.
nxpfan 5:84e6c89a9a6d 326 * * Loop unrolled. minimized loop overhead
nxpfan 5:84e6c89a9a6d 327 */
nxpfan 5:84e6c89a9a6d 328 #if ( LINE_READ_OPT == LOOP_UNROLL )
nxpfan 5:84e6c89a9a6d 329
nxpfan 5:84e6c89a9a6d 330 char reg = COMMAND_READ | CAMERA_DATA_REGISTER | COMMAND_ADDR_INCREMENT;
nxpfan 5:84e6c89a9a6d 331
nxpfan 5:84e6c89a9a6d 332 if ( _read_order_change ) {
nxpfan 5:84e6c89a9a6d 333
nxpfan 3:7f26004cfbce 334 _cs = 0;
nxpfan 5:84e6c89a9a6d 335
nxpfan 1:b2324313d4da 336 for( int x = 0; x < n_of_pixels; x += 8 ) {
nxpfan 1:b2324313d4da 337 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
nxpfan 5:84e6c89a9a6d 338
nxpfan 5:84e6c89a9a6d 339 *p = _spi.write( reg );
nxpfan 5:84e6c89a9a6d 340 *p++ |= _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 341
nxpfan 5:84e6c89a9a6d 342 *p = _spi.write( reg );
nxpfan 5:84e6c89a9a6d 343 *p++ |= _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 344
nxpfan 5:84e6c89a9a6d 345 *p = _spi.write( reg );
nxpfan 5:84e6c89a9a6d 346 *p++ |= _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 347
nxpfan 5:84e6c89a9a6d 348 *p = _spi.write( reg );
nxpfan 5:84e6c89a9a6d 349 *p++ |= _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 350
nxpfan 5:84e6c89a9a6d 351 *p = _spi.write( reg );
nxpfan 5:84e6c89a9a6d 352 *p++ |= _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 353
nxpfan 5:84e6c89a9a6d 354 *p = _spi.write( reg );
nxpfan 5:84e6c89a9a6d 355 *p++ |= _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 356
nxpfan 5:84e6c89a9a6d 357 *p = _spi.write( reg );
nxpfan 5:84e6c89a9a6d 358 *p++ |= _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 359
nxpfan 5:84e6c89a9a6d 360 *p = _spi.write( reg );
nxpfan 5:84e6c89a9a6d 361 *p++ |= _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 362
nxpfan 1:b2324313d4da 363 }
nxpfan 3:7f26004cfbce 364 _cs = 1;
nxpfan 5:84e6c89a9a6d 365
nxpfan 5:84e6c89a9a6d 366 } else {
nxpfan 5:84e6c89a9a6d 367
nxpfan 5:84e6c89a9a6d 368 read_register( CAMERA_DATA_REGISTER );
nxpfan 5:84e6c89a9a6d 369
nxpfan 5:84e6c89a9a6d 370 _cs = 0;
nxpfan 5:84e6c89a9a6d 371
nxpfan 5:84e6c89a9a6d 372 for( int x = 0; x < n_of_pixels; x += 8 ) {
nxpfan 0:c4d14dd5d479 373 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
nxpfan 5:84e6c89a9a6d 374
nxpfan 5:84e6c89a9a6d 375 *p = _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 376 *p++ |= _spi.write( reg );
nxpfan 5:84e6c89a9a6d 377
nxpfan 5:84e6c89a9a6d 378 *p = _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 379 *p++ |= _spi.write( reg );
nxpfan 5:84e6c89a9a6d 380
nxpfan 5:84e6c89a9a6d 381 *p = _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 382 *p++ |= _spi.write( reg );
nxpfan 5:84e6c89a9a6d 383
nxpfan 5:84e6c89a9a6d 384 *p = _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 385 *p++ |= _spi.write( reg );
nxpfan 5:84e6c89a9a6d 386
nxpfan 5:84e6c89a9a6d 387 *p = _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 388 *p++ |= _spi.write( reg );
nxpfan 5:84e6c89a9a6d 389
nxpfan 5:84e6c89a9a6d 390 *p = _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 391 *p++ |= _spi.write( reg );
nxpfan 5:84e6c89a9a6d 392
nxpfan 5:84e6c89a9a6d 393 *p = _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 394 *p++ |= _spi.write( reg );
nxpfan 5:84e6c89a9a6d 395
nxpfan 5:84e6c89a9a6d 396 *p = _spi.write( reg ) << 8;
nxpfan 5:84e6c89a9a6d 397 *p++ |= _spi.write( reg );
nxpfan 5:84e6c89a9a6d 398
nxpfan 0:c4d14dd5d479 399 }
nxpfan 5:84e6c89a9a6d 400 _cs = 1;
nxpfan 0:c4d14dd5d479 401 }
nxpfan 5:84e6c89a9a6d 402 #endif // ( LINE_READ_OPT == LOOP_UNROLL )
nxpfan 4:8ef31b67c0ab 403
nxpfan 4:8ef31b67c0ab 404
nxpfan 5:84e6c89a9a6d 405 /*
nxpfan 5:84e6c89a9a6d 406 * Type2: "LINE_READ_OPT" is define as "USING_SSP_FIFO"
nxpfan 5:84e6c89a9a6d 407 * Fastest but no compatibility with mbed-SDK.
nxpfan 5:84e6c89a9a6d 408 * The optimization has been done to use FIFO of SSP block.
nxpfan 5:84e6c89a9a6d 409 * This code makes data transfer efficiency maximum.
nxpfan 5:84e6c89a9a6d 410 * However, since this optimization is done in very low level (by register accessing),
nxpfan 5:84e6c89a9a6d 411 * it works on some MCU's only (test has been done on LPC1768, LPC11U24 and LPC11U35).
nxpfan 5:84e6c89a9a6d 412 *
nxpfan 5:84e6c89a9a6d 413 * And user need to care about which SSP block is used. For instance, if the SPI pins
nxpfan 5:84e6c89a9a6d 414 * of p5, p6 and p7 are used, those are connected to SSP1 in LPC1768. In case of
nxpfan 5:84e6c89a9a6d 415 * LPC11U24 and LPC11U35, those pins are routed to SSP0.
nxpfan 5:84e6c89a9a6d 416 * These settings should be done manually
nxpfan 5:84e6c89a9a6d 417 */
nxpfan 5:84e6c89a9a6d 418 #if ( LINE_READ_OPT == USING_SSP_FIFO )
nxpfan 4:8ef31b67c0ab 419
nxpfan 5:84e6c89a9a6d 420 #define FIFO_DEPTH 4
nxpfan 4:8ef31b67c0ab 421
nxpfan 5:84e6c89a9a6d 422 #if defined( SSP_AUTO_SELECTION )
nxpfan 5:84e6c89a9a6d 423 #if defined( TARGET_MBED_LPC1768 )
nxpfan 5:84e6c89a9a6d 424 #define SPI_PORT_SELECTOR LPC_SSP1
nxpfan 5:84e6c89a9a6d 425 #elif defined( TARGET_LPC11U35_501 ) || defined( TARGET_LPC11U24_401 )
nxpfan 5:84e6c89a9a6d 426 #define SPI_PORT_SELECTOR LPC_SSP0
nxpfan 5:84e6c89a9a6d 427 #endif
nxpfan 5:84e6c89a9a6d 428 #elif defined( SSP_USE_SSP0 )
nxpfan 5:84e6c89a9a6d 429 #define SPI_PORT_SELECTOR LPC_SSP0
nxpfan 5:84e6c89a9a6d 430 #elif defined( SSP_USE_SSP1 )
nxpfan 5:84e6c89a9a6d 431 #define SPI_PORT_SELECTOR LPC_SSP1
nxpfan 5:84e6c89a9a6d 432 #else
nxpfan 5:84e6c89a9a6d 433 #error when using FIFO option for the optimization, choose one of definition from SSP_AUTO_SELECTION, SSP_USE_SSP0 or SSP_USE_SSP1
nxpfan 5:84e6c89a9a6d 434 #endif // #if defined( SSP_AUTO_SELECTION )
nxpfan 4:8ef31b67c0ab 435
nxpfan 5:84e6c89a9a6d 436 char reg = COMMAND_READ | CAMERA_DATA_REGISTER | COMMAND_ADDR_INCREMENT;
nxpfan 5:84e6c89a9a6d 437 int n;
nxpfan 4:8ef31b67c0ab 438
nxpfan 4:8ef31b67c0ab 439 if ( _read_order_change ) {
nxpfan 5:84e6c89a9a6d 440
nxpfan 4:8ef31b67c0ab 441 _cs = 0;
nxpfan 4:8ef31b67c0ab 442
nxpfan 4:8ef31b67c0ab 443 for(n = FIFO_DEPTH; n > 0; n--) {
nxpfan 4:8ef31b67c0ab 444 SPI_PORT_SELECTOR->DR = reg;
nxpfan 4:8ef31b67c0ab 445 }
nxpfan 4:8ef31b67c0ab 446
nxpfan 4:8ef31b67c0ab 447 do {
nxpfan 4:8ef31b67c0ab 448 while (!(SPI_PORT_SELECTOR->SR & 0x4));
nxpfan 4:8ef31b67c0ab 449 *p = (SPI_PORT_SELECTOR->DR & 0xFF);
nxpfan 4:8ef31b67c0ab 450
nxpfan 4:8ef31b67c0ab 451 if (n++ < (n_of_pixels << 1) - FIFO_DEPTH)
nxpfan 4:8ef31b67c0ab 452 SPI_PORT_SELECTOR->DR = reg;
nxpfan 4:8ef31b67c0ab 453
nxpfan 4:8ef31b67c0ab 454 while (!(SPI_PORT_SELECTOR->SR & 0x4));
nxpfan 4:8ef31b67c0ab 455 *p++ |= (SPI_PORT_SELECTOR->DR << 8);
nxpfan 4:8ef31b67c0ab 456
nxpfan 4:8ef31b67c0ab 457 if (n++ < (n_of_pixels << 1) - FIFO_DEPTH)
nxpfan 4:8ef31b67c0ab 458 SPI_PORT_SELECTOR->DR = reg;
nxpfan 4:8ef31b67c0ab 459
nxpfan 4:8ef31b67c0ab 460 } while(n < (n_of_pixels << 1));
nxpfan 4:8ef31b67c0ab 461
nxpfan 4:8ef31b67c0ab 462 _cs = 1;
nxpfan 5:84e6c89a9a6d 463
nxpfan 4:8ef31b67c0ab 464 } else {
nxpfan 5:84e6c89a9a6d 465
nxpfan 4:8ef31b67c0ab 466 read_register( CAMERA_DATA_REGISTER );
nxpfan 4:8ef31b67c0ab 467
nxpfan 4:8ef31b67c0ab 468 _cs = 0;
nxpfan 4:8ef31b67c0ab 469
nxpfan 4:8ef31b67c0ab 470 for(n = FIFO_DEPTH; n > 0; n--) {
nxpfan 4:8ef31b67c0ab 471 SPI_PORT_SELECTOR->DR = reg;
nxpfan 4:8ef31b67c0ab 472 }
nxpfan 4:8ef31b67c0ab 473
nxpfan 4:8ef31b67c0ab 474 do {
nxpfan 4:8ef31b67c0ab 475 while (!(SPI_PORT_SELECTOR->SR & 0x4));
nxpfan 4:8ef31b67c0ab 476 *p = (SPI_PORT_SELECTOR->DR << 8);
nxpfan 4:8ef31b67c0ab 477
nxpfan 4:8ef31b67c0ab 478 if (n++ < (n_of_pixels << 1) - FIFO_DEPTH)
nxpfan 4:8ef31b67c0ab 479 SPI_PORT_SELECTOR->DR = reg;
nxpfan 4:8ef31b67c0ab 480
nxpfan 4:8ef31b67c0ab 481 while (!(SPI_PORT_SELECTOR->SR & 0x4));
nxpfan 4:8ef31b67c0ab 482 *p++ |= (SPI_PORT_SELECTOR->DR & 0xFF);
nxpfan 4:8ef31b67c0ab 483
nxpfan 4:8ef31b67c0ab 484 if (n++ < (n_of_pixels << 1) - FIFO_DEPTH)
nxpfan 4:8ef31b67c0ab 485 SPI_PORT_SELECTOR->DR = reg;
nxpfan 4:8ef31b67c0ab 486
nxpfan 4:8ef31b67c0ab 487 } while(n < (n_of_pixels << 1));
nxpfan 4:8ef31b67c0ab 488
nxpfan 4:8ef31b67c0ab 489 _cs = 1;
nxpfan 4:8ef31b67c0ab 490 }
nxpfan 5:84e6c89a9a6d 491
nxpfan 5:84e6c89a9a6d 492 #endif // ( LINE_READ_OPT == USING_SSP_FIFO )
nxpfan 4:8ef31b67c0ab 493 }
nxpfan 4:8ef31b67c0ab 494
nxpfan 0:c4d14dd5d479 495 void MARMEX_VB::open_transfer( void )
nxpfan 0:c4d14dd5d479 496 {
nxpfan 0:c4d14dd5d479 497 // send command to pause the camera buffer update
nxpfan 0:c4d14dd5d479 498 write_register( CONTROL_DATA_REGISTER, CONTROL__PAUSE_BUFFER_UPDATE );
nxpfan 0:c4d14dd5d479 499
nxpfan 0:c4d14dd5d479 500 // read status register (first return byte should be ignored)
nxpfan 0:c4d14dd5d479 501 read_register( STATUS_REGISTER );
nxpfan 0:c4d14dd5d479 502
nxpfan 0:c4d14dd5d479 503 // wait until the status register become 0x51(ready to transfer data)
nxpfan 0:c4d14dd5d479 504 while ( 0x51 != read_register( STATUS_REGISTER ) )
nxpfan 0:c4d14dd5d479 505 ;
nxpfan 0:c4d14dd5d479 506 }
nxpfan 0:c4d14dd5d479 507
nxpfan 0:c4d14dd5d479 508 void MARMEX_VB::close_transfer( void )
nxpfan 0:c4d14dd5d479 509 {
nxpfan 0:c4d14dd5d479 510 // send command to resume the camera buffer update
nxpfan 0:c4d14dd5d479 511 write_register( CONTROL_DATA_REGISTER, CONTROL__RESUME_BUFFER_UPDATE );
nxpfan 0:c4d14dd5d479 512
nxpfan 0:c4d14dd5d479 513 // read status register (first return byte should be ignored)
nxpfan 0:c4d14dd5d479 514 read_register( STATUS_REGISTER );
nxpfan 0:c4d14dd5d479 515
nxpfan 0:c4d14dd5d479 516 // wait until the status register become 0x50(camera updating the buffer)
nxpfan 0:c4d14dd5d479 517 while ( 0x50 != read_register( STATUS_REGISTER ) )
nxpfan 0:c4d14dd5d479 518 ;
nxpfan 0:c4d14dd5d479 519 }
nxpfan 0:c4d14dd5d479 520
nxpfan 0:c4d14dd5d479 521 int MARMEX_VB::read_order_change( void )
nxpfan 0:c4d14dd5d479 522 {
nxpfan 0:c4d14dd5d479 523 return ( _read_order_change = !_read_order_change );
nxpfan 0:c4d14dd5d479 524 }
nxpfan 0:c4d14dd5d479 525
nxpfan 0:c4d14dd5d479 526 void MARMEX_VB::set_address( int address )
nxpfan 0:c4d14dd5d479 527 {
nxpfan 0:c4d14dd5d479 528 // set memory address (3 bytes)
nxpfan 0:c4d14dd5d479 529
nxpfan 0:c4d14dd5d479 530 write_register( MEMORY_ADDR_LOW__REGISTER, (address >> 0) & 0xFF );
nxpfan 0:c4d14dd5d479 531 write_register( MEMORY_ADDR_MID__REGISTER, (address >> 8) & 0xFF );
nxpfan 0:c4d14dd5d479 532 write_register( MEMORY_ADDR_HIGH_REGISTER, (address >> 16) & 0xFF );
nxpfan 0:c4d14dd5d479 533 }
nxpfan 0:c4d14dd5d479 534
nxpfan 0:c4d14dd5d479 535 void MARMEX_VB::write_register( char reg, char value )
nxpfan 0:c4d14dd5d479 536 {
nxpfan 0:c4d14dd5d479 537 // camera register write
nxpfan 0:c4d14dd5d479 538
nxpfan 0:c4d14dd5d479 539 send_spi( COMMAND_WRITE | reg ); // send command and register number
nxpfan 0:c4d14dd5d479 540 send_spi( value ); // send register value
nxpfan 0:c4d14dd5d479 541 }
nxpfan 0:c4d14dd5d479 542
nxpfan 0:c4d14dd5d479 543 int MARMEX_VB::read_register( char reg )
nxpfan 0:c4d14dd5d479 544 {
nxpfan 0:c4d14dd5d479 545 // camera register read
nxpfan 0:c4d14dd5d479 546 // returning current data in SPI buffer (data returned by previous command)
nxpfan 0:c4d14dd5d479 547
nxpfan 0:c4d14dd5d479 548 return ( send_spi( COMMAND_READ | reg | ((reg == CAMERA_DATA_REGISTER) ? COMMAND_ADDR_INCREMENT : 0x00) ) );
nxpfan 0:c4d14dd5d479 549 }
nxpfan 0:c4d14dd5d479 550
nxpfan 0:c4d14dd5d479 551 int MARMEX_VB::send_spi( char data )
nxpfan 0:c4d14dd5d479 552 {
nxpfan 0:c4d14dd5d479 553 int tmp;
nxpfan 0:c4d14dd5d479 554
nxpfan 0:c4d14dd5d479 555 // SPI access
nxpfan 0:c4d14dd5d479 556 _cs = 0;
nxpfan 0:c4d14dd5d479 557 tmp = _spi.write( data );
nxpfan 0:c4d14dd5d479 558 _cs = 1;
nxpfan 0:c4d14dd5d479 559
nxpfan 0:c4d14dd5d479 560 return ( tmp );
nxpfan 0:c4d14dd5d479 561 }