Added support for the WNC M14A2A Cellular LTE Data Module.

Dependencies:   WNC14A2AInterface

Easy Connect

Easily add all supported connectivity methods to your mbed OS project

This project is derived from https://developer.mbed.org/teams/sandbox/code/simple-mbed-client-example/file/dd6231df71bb/easy-connect.lib. It give user the ability to switch between connectivity methods and includes support for the WNC14A2A Data Module. The `NetworkInterface` API makes this easy, but you still need a mechanism for the user to select the connection method, The selection is made by modifying the `mbed_app.json` file and using `easy_connect()` from your application.

Specifying connectivity method

To add support for the WNC14A2A, add the following to your ``mbed_app.json`` file:

mbed_app.json

{
    "config": {
        "network-interface":{
            "help": "options are ETHERNET,WIFI_ESP8266,WIFI_ODIN,MESH_LOWPAN_ND,MESH_THREAD,WNC14A2A",
            "value": "WNC14A2A"
        }
    },
}

After you choose `WNC14A2A` you'll also need to indicate if you want debug output or not by Enabling (true) or Disabling (false) WNC_DEBUG.

If WNC_DEBUG is enabled, there are 3 different levels of debug output (selected via bit settings). These debug levels are set using the following values:

ValueDescription
1Basic WNC driver debug output
2Comprehensive WNC driver debug output
4Network Layer debug output

You can have any combination of these three bit values for a total value of 0 – 7.

WNC Debug Settings

    "config": {
        "WNC_DEBUG": {
            "value": false
        },
        "WNC_DEBUG_SETTING": {
            "value": 4
        },
    }

Using Easy Connect from your application

Easy Connect has just one function which will either return a `NetworkInterface`-pointer or `NULL`:

Sample Code

#include "easy-connect.h"

int main(int, char**) {
    NetworkInterface* network = easy_connect(true); /* has 1 argument, enable_logging (pass in true to log to serial port) */
    if (!network) {
        printf("Connecting to the network failed... See serial output.\r\n");
        return 1;
    }
 
    // Rest of your program
}

Tested on

  • K64F with Ethernet.
  • AT&T Cellular IoT Starter Kit with WNC M14A2A Cellular Data Module

The WNCInterface class currently supports the following version(s):

  • MPSS: M14A2A_v11.50.164451 APSS: M14A2A_v11.53.164451

License

This library is released under the Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License and may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Committer:
group-Avnet
Date:
Wed Apr 19 01:08:11 2017 +0000
Revision:
0:478cfd88041f
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-Avnet 0:478cfd88041f 1 /**
group-Avnet 0:478cfd88041f 2 ******************************************************************************
group-Avnet 0:478cfd88041f 3 * @file SPIRIT_Regs.h
group-Avnet 0:478cfd88041f 4 * @author VMA division - AMS
group-Avnet 0:478cfd88041f 5 * @version 3.2.2
group-Avnet 0:478cfd88041f 6 * @date 08-July-2015
group-Avnet 0:478cfd88041f 7 * @brief This file contains all the SPIRIT registers address and masks.
group-Avnet 0:478cfd88041f 8 * @details
group-Avnet 0:478cfd88041f 9 *
group-Avnet 0:478cfd88041f 10 * @attention
group-Avnet 0:478cfd88041f 11 *
group-Avnet 0:478cfd88041f 12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
group-Avnet 0:478cfd88041f 13 *
group-Avnet 0:478cfd88041f 14 * Redistribution and use in source and binary forms, with or without modification,
group-Avnet 0:478cfd88041f 15 * are permitted provided that the following conditions are met:
group-Avnet 0:478cfd88041f 16 * 1. Redistributions of source code must retain the above copyright notice,
group-Avnet 0:478cfd88041f 17 * this list of conditions and the following disclaimer.
group-Avnet 0:478cfd88041f 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
group-Avnet 0:478cfd88041f 19 * this list of conditions and the following disclaimer in the documentation
group-Avnet 0:478cfd88041f 20 * and/or other materials provided with the distribution.
group-Avnet 0:478cfd88041f 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
group-Avnet 0:478cfd88041f 22 * may be used to endorse or promote products derived from this software
group-Avnet 0:478cfd88041f 23 * without specific prior written permission.
group-Avnet 0:478cfd88041f 24 *
group-Avnet 0:478cfd88041f 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-Avnet 0:478cfd88041f 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-Avnet 0:478cfd88041f 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-Avnet 0:478cfd88041f 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
group-Avnet 0:478cfd88041f 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
group-Avnet 0:478cfd88041f 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
group-Avnet 0:478cfd88041f 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
group-Avnet 0:478cfd88041f 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
group-Avnet 0:478cfd88041f 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
group-Avnet 0:478cfd88041f 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-Avnet 0:478cfd88041f 35 *
group-Avnet 0:478cfd88041f 36 ******************************************************************************
group-Avnet 0:478cfd88041f 37 */
group-Avnet 0:478cfd88041f 38
group-Avnet 0:478cfd88041f 39 /* Define to prevent recursive inclusion -------------------------------------*/
group-Avnet 0:478cfd88041f 40 #ifndef __SPIRIT1_REGS_H
group-Avnet 0:478cfd88041f 41 #define __SPIRIT1_REGS_H
group-Avnet 0:478cfd88041f 42
group-Avnet 0:478cfd88041f 43 #ifdef __cplusplus
group-Avnet 0:478cfd88041f 44 extern "C" {
group-Avnet 0:478cfd88041f 45 #endif
group-Avnet 0:478cfd88041f 46
group-Avnet 0:478cfd88041f 47 /**
group-Avnet 0:478cfd88041f 48 * @addtogroup SPIRIT_Registers SPIRIT Registers
group-Avnet 0:478cfd88041f 49 * @brief Header file containing all the SPIRIT registers address and masks.
group-Avnet 0:478cfd88041f 50 * @details See the file <i>@ref SPIRIT_Regs.h</i> for more details.
group-Avnet 0:478cfd88041f 51 * @{
group-Avnet 0:478cfd88041f 52 */
group-Avnet 0:478cfd88041f 53
group-Avnet 0:478cfd88041f 54 /** @defgroup General_Configuration_Registers
group-Avnet 0:478cfd88041f 55 * @{
group-Avnet 0:478cfd88041f 56 */
group-Avnet 0:478cfd88041f 57
group-Avnet 0:478cfd88041f 58 /** @defgroup ANA_FUNC_CONF_1_Register
group-Avnet 0:478cfd88041f 59 * @{
group-Avnet 0:478cfd88041f 60 */
group-Avnet 0:478cfd88041f 61
group-Avnet 0:478cfd88041f 62 /**
group-Avnet 0:478cfd88041f 63 * \brief ANA_FUNC_CONF register 1
group-Avnet 0:478cfd88041f 64 * \code
group-Avnet 0:478cfd88041f 65 * Read Write
group-Avnet 0:478cfd88041f 66 * Default value: 0x0C
group-Avnet 0:478cfd88041f 67 * 7:5 NUM_EN_PIPES: Number of enabled pipes (starting from Data Pipe 0).
group-Avnet 0:478cfd88041f 68 * 4:2 GM_CONF[2:0]: Sets the driver gm of the XO at start-up:
group-Avnet 0:478cfd88041f 69 * GM_CONF2 | GM_CONF1 | GM_CONF0 | GM [mS]
group-Avnet 0:478cfd88041f 70 * ------------------------------------------
group-Avnet 0:478cfd88041f 71 * 0 | 0 | 0 | 13.2
group-Avnet 0:478cfd88041f 72 * 0 | 0 | 1 | 18.2
group-Avnet 0:478cfd88041f 73 * 0 | 1 | 0 | 21.5
group-Avnet 0:478cfd88041f 74 * 0 | 1 | 1 | 25.6
group-Avnet 0:478cfd88041f 75 * 1 | 0 | 0 | 28.8
group-Avnet 0:478cfd88041f 76 * 1 | 0 | 1 | 33.9
group-Avnet 0:478cfd88041f 77 * 1 | 1 | 0 | 38.5
group-Avnet 0:478cfd88041f 78 * 1 | 1 | 1 | 43.0
group-Avnet 0:478cfd88041f 79 * 1:0 SET_BLD_LVL[1:0]: Sets the Battery Level Detector threshold:
group-Avnet 0:478cfd88041f 80 * SET_BLD_LVL1 | SET_BLD_LVL0 | Threshold [V]
group-Avnet 0:478cfd88041f 81 * ------------------------------------------
group-Avnet 0:478cfd88041f 82 * 0 | 0 | 2.7
group-Avnet 0:478cfd88041f 83 * 0 | 1 | 2.5
group-Avnet 0:478cfd88041f 84 * 1 | 0 | 2.3
group-Avnet 0:478cfd88041f 85 * 1 | 1 | 2.1
group-Avnet 0:478cfd88041f 86 * \endcode
group-Avnet 0:478cfd88041f 87 */
group-Avnet 0:478cfd88041f 88
group-Avnet 0:478cfd88041f 89 #define ANA_FUNC_CONF1_BASE ((uint8_t)0x00) /*!< ANA_FUNC_CONF1 Address (R/W) */
group-Avnet 0:478cfd88041f 90
group-Avnet 0:478cfd88041f 91 #define ANA_FUNC_CONF1_NUM_PIPES_MASK ((uint8_t)0xE0) /*!< Mask for number of enabled pipes*/
group-Avnet 0:478cfd88041f 92
group-Avnet 0:478cfd88041f 93 #define ANA_FUNC_CONF1_GMCONF_MASK ((uint8_t)0x1C) /*!< Mask of the GmConf field of ANA_FUNC_CONF1 register (R/W) */
group-Avnet 0:478cfd88041f 94
group-Avnet 0:478cfd88041f 95 #define GM_13_2 ((uint8_t)0x00) /*!< Transconducatance Gm at start-up 13.2 mS */
group-Avnet 0:478cfd88041f 96 #define GM_18_2 ((uint8_t)0x04) /*!< Transconducatance Gm at start-up 18.2 mS */
group-Avnet 0:478cfd88041f 97 #define GM_21_5 ((uint8_t)0x08) /*!< Transconducatance Gm at start-up 21.5 mS */
group-Avnet 0:478cfd88041f 98 #define GM_25_6 ((uint8_t)0x0C) /*!< Transconducatance Gm at start-up 25.6 mS */
group-Avnet 0:478cfd88041f 99 #define GM_28_8 ((uint8_t)0x10) /*!< Transconducatance Gm at start-up 28.8 mS */
group-Avnet 0:478cfd88041f 100 #define GM_33_9 ((uint8_t)0x14) /*!< Transconducatance Gm at start-up 33.9 mS */
group-Avnet 0:478cfd88041f 101 #define GM_38_5 ((uint8_t)0x18) /*!< Transconducatance Gm at start-up 38.5 mS */
group-Avnet 0:478cfd88041f 102 #define GM_43_0 ((uint8_t)0x1C) /*!< Transconducatance Gm at start-up 43.0 mS */
group-Avnet 0:478cfd88041f 103
group-Avnet 0:478cfd88041f 104 #define ANA_FUNC_CONF1_SET_BLD_LVL_MASK ((uint8_t)0x03) /*!< Mask of the SET_BLD_LV field of ANA_FUNC_CONF1 register (R/W) */
group-Avnet 0:478cfd88041f 105
group-Avnet 0:478cfd88041f 106 #define BLD_LVL_2_7 ((uint8_t)0x00) /*!< Sets the Battery Level Detector threshold to 2.7V */
group-Avnet 0:478cfd88041f 107 #define BLD_LVL_2_5 ((uint8_t)0x01) /*!< Sets the Battery Level Detector threshold to 2.5V */
group-Avnet 0:478cfd88041f 108 #define BLD_LVL_2_3 ((uint8_t)0x02) /*!< Sets the Battery Level Detector threshold to 2.3V */
group-Avnet 0:478cfd88041f 109 #define BLD_LVL_2_1 ((uint8_t)0x03) /*!< Sets the Battery Level Detector threshold to 2.1V */
group-Avnet 0:478cfd88041f 110
group-Avnet 0:478cfd88041f 111 /**
group-Avnet 0:478cfd88041f 112 * @}
group-Avnet 0:478cfd88041f 113 */
group-Avnet 0:478cfd88041f 114
group-Avnet 0:478cfd88041f 115
group-Avnet 0:478cfd88041f 116 /** @defgroup ANA_FUNC_CONF_0_Register
group-Avnet 0:478cfd88041f 117 * @{
group-Avnet 0:478cfd88041f 118 */
group-Avnet 0:478cfd88041f 119
group-Avnet 0:478cfd88041f 120 /**
group-Avnet 0:478cfd88041f 121 * \brief ANA_FUNC_CONF register 0
group-Avnet 0:478cfd88041f 122 * \code
group-Avnet 0:478cfd88041f 123 * Read Write
group-Avnet 0:478cfd88041f 124 * Default value: 0xC0
group-Avnet 0:478cfd88041f 125 * 7 Reserved.
group-Avnet 0:478cfd88041f 126 * 6 24_26_MHz_SELECT: 1 - 26 MHz configuration
group-Avnet 0:478cfd88041f 127 * 0 - 24 MHz configuration
group-Avnet 0:478cfd88041f 128 * 5 AES_ON: 1 - AES engine enabled
group-Avnet 0:478cfd88041f 129 * 0 - AES engine disabled
group-Avnet 0:478cfd88041f 130 * 4 EXT_REF: 1 - Reference signal from XIN pin
group-Avnet 0:478cfd88041f 131 * 0 - Reference signal from XO circuit
group-Avnet 0:478cfd88041f 132 * 3 HIGH_POWER_MODE: 1 - SET_SMPS_LEVEL word will be set to the value to
group-Avnet 0:478cfd88041f 133 * PM_TEST register in RX state, while in TX state it
group-Avnet 0:478cfd88041f 134 * will be fixed to 111 (which programs the SMPS output
group-Avnet 0:478cfd88041f 135 * at max value 1.8V)
group-Avnet 0:478cfd88041f 136 * 0 - SET_SMPS_LEVEL word will hold the value written in the
group-Avnet 0:478cfd88041f 137 * PM_TEST register both in RX and TX state
group-Avnet 0:478cfd88041f 138 * 2 BROWN_OUT: 1 - Brown_Out Detection enabled
group-Avnet 0:478cfd88041f 139 * 0 - Brown_Out Detection disabled
group-Avnet 0:478cfd88041f 140 * 1 BATTERY_LEVEL: 1 - Battery level detector enabled
group-Avnet 0:478cfd88041f 141 * 0 - Battery level detector disabled
group-Avnet 0:478cfd88041f 142 * 0 TS: 1 - Enable the "Temperature Sensor" function
group-Avnet 0:478cfd88041f 143 * 0 - Disable the "Temperature Sensor" function
group-Avnet 0:478cfd88041f 144 * \endcode
group-Avnet 0:478cfd88041f 145 */
group-Avnet 0:478cfd88041f 146
group-Avnet 0:478cfd88041f 147
group-Avnet 0:478cfd88041f 148 #define ANA_FUNC_CONF0_BASE ((uint8_t)0x01) /*!< ANA_FUNC_CONF0 Address (R/W) */
group-Avnet 0:478cfd88041f 149
group-Avnet 0:478cfd88041f 150 #define SELECT_24_26_MHZ_MASK ((uint8_t)0x40) /*!< Configure the RCO if using 26 MHz or 24 MHz master clock/reference signal */
group-Avnet 0:478cfd88041f 151 #define AES_MASK ((uint8_t)0x20) /*!< AES engine on/off */
group-Avnet 0:478cfd88041f 152 #define EXT_REF_MASK ((uint8_t)0x10) /*!< Reference signal from XIN pin (oscillator external) or from XO circuit (oscillator internal)*/
group-Avnet 0:478cfd88041f 153 #define HIGH_POWER_MODE_MASK ((uint8_t)0x08) /*!< SET_SMPS_LEVEL word will be set to the value to PM_TEST register
group-Avnet 0:478cfd88041f 154 in RX state, while in TX state it will be fixed to 111
group-Avnet 0:478cfd88041f 155 (which programs the SMPS output at max value, 1.8V) */
group-Avnet 0:478cfd88041f 156 #define BROWN_OUT_MASK ((uint8_t)0x04) /*!< Accurate Brown-Out detection on/off */
group-Avnet 0:478cfd88041f 157 #define BATTERY_LEVEL_MASK ((uint8_t)0x02) /*!< Battery level detector circuit on/off */
group-Avnet 0:478cfd88041f 158 #define TEMPERATURE_SENSOR_MASK ((uint8_t)0x01) /*!< The Temperature Sensor (available on GPIO0) on/off */
group-Avnet 0:478cfd88041f 159
group-Avnet 0:478cfd88041f 160 /**
group-Avnet 0:478cfd88041f 161 * @}
group-Avnet 0:478cfd88041f 162 */
group-Avnet 0:478cfd88041f 163
group-Avnet 0:478cfd88041f 164 /** @defgroup ANT_SELECT_CONF_Register
group-Avnet 0:478cfd88041f 165 * @{
group-Avnet 0:478cfd88041f 166 */
group-Avnet 0:478cfd88041f 167
group-Avnet 0:478cfd88041f 168 /**
group-Avnet 0:478cfd88041f 169 * \brief ANT_SELECT_CONF register
group-Avnet 0:478cfd88041f 170 * \code
group-Avnet 0:478cfd88041f 171 * Read Write
group-Avnet 0:478cfd88041f 172 * Default value: 0x05
group-Avnet 0:478cfd88041f 173 *
group-Avnet 0:478cfd88041f 174 * 7:5 Reserved.
group-Avnet 0:478cfd88041f 175 *
group-Avnet 0:478cfd88041f 176 * 4 CS_BLANKING: Blank received data if signal is below the CS threshold
group-Avnet 0:478cfd88041f 177 *
group-Avnet 0:478cfd88041f 178 * 3 AS_ENABLE: Enable antenna switching
group-Avnet 0:478cfd88041f 179 * 1 - Enable
group-Avnet 0:478cfd88041f 180 * 0 - Disable
group-Avnet 0:478cfd88041f 181 *
group-Avnet 0:478cfd88041f 182 * 2:0 AS_MEAS_TIME[2:0]: Measurement time according to the formula Tmeas = 24*2^(EchFlt)*2^AS_MEAS_TIME/fxo
group-Avnet 0:478cfd88041f 183 * \endcode
group-Avnet 0:478cfd88041f 184 */
group-Avnet 0:478cfd88041f 185 #define ANT_SELECT_CONF_BASE ((uint8_t)0x27) /*!< Antenna diversity (works only in static carrier sense mode) */
group-Avnet 0:478cfd88041f 186 #define ANT_SELECT_CS_BLANKING_MASK ((uint8_t)0x10) /*!< CS data blanking on/off */
group-Avnet 0:478cfd88041f 187 #define ANT_SELECT_CONF_AS_MASK ((uint8_t)0x08) /*!< Antenna diversity on/off */
group-Avnet 0:478cfd88041f 188
group-Avnet 0:478cfd88041f 189 /**
group-Avnet 0:478cfd88041f 190 * @}
group-Avnet 0:478cfd88041f 191 */
group-Avnet 0:478cfd88041f 192
group-Avnet 0:478cfd88041f 193 /** @defgroup DEVICE_INFO1_Register
group-Avnet 0:478cfd88041f 194 * @{
group-Avnet 0:478cfd88041f 195 */
group-Avnet 0:478cfd88041f 196
group-Avnet 0:478cfd88041f 197 /**
group-Avnet 0:478cfd88041f 198 * \brief DEVICE_INFO1[7:0] registers
group-Avnet 0:478cfd88041f 199 * \code
group-Avnet 0:478cfd88041f 200 * Default value: 0x01
group-Avnet 0:478cfd88041f 201 * Read
group-Avnet 0:478cfd88041f 202 *
group-Avnet 0:478cfd88041f 203 * 7:0 PARTNUM[7:0]: Device part number
group-Avnet 0:478cfd88041f 204 * \endcode
group-Avnet 0:478cfd88041f 205 */
group-Avnet 0:478cfd88041f 206 #define DEVICE_INFO1_PARTNUM ((uint8_t)(0xF0)) /*!< Device part number [7:0] */
group-Avnet 0:478cfd88041f 207
group-Avnet 0:478cfd88041f 208 /**
group-Avnet 0:478cfd88041f 209 * @}
group-Avnet 0:478cfd88041f 210 */
group-Avnet 0:478cfd88041f 211
group-Avnet 0:478cfd88041f 212 /** @defgroup DEVICE_INFO0_Register
group-Avnet 0:478cfd88041f 213 * @{
group-Avnet 0:478cfd88041f 214 */
group-Avnet 0:478cfd88041f 215
group-Avnet 0:478cfd88041f 216 /**
group-Avnet 0:478cfd88041f 217 * \brief DEVICE_INFO0[7:0] registers
group-Avnet 0:478cfd88041f 218 * \code
group-Avnet 0:478cfd88041f 219 * Read
group-Avnet 0:478cfd88041f 220 *
group-Avnet 0:478cfd88041f 221 * 7:0 VERSION[7:0]: Device version number
group-Avnet 0:478cfd88041f 222 * \endcode
group-Avnet 0:478cfd88041f 223 */
group-Avnet 0:478cfd88041f 224 #define DEVICE_INFO0_VERSION ((uint8_t)(0xF1)) /*!< Device version [7:0]; (0x55 in CUT1.0) */
group-Avnet 0:478cfd88041f 225
group-Avnet 0:478cfd88041f 226 /**
group-Avnet 0:478cfd88041f 227 * @}
group-Avnet 0:478cfd88041f 228 */
group-Avnet 0:478cfd88041f 229
group-Avnet 0:478cfd88041f 230
group-Avnet 0:478cfd88041f 231 /**
group-Avnet 0:478cfd88041f 232 * @}
group-Avnet 0:478cfd88041f 233 */
group-Avnet 0:478cfd88041f 234
group-Avnet 0:478cfd88041f 235
group-Avnet 0:478cfd88041f 236 /** @defgroup GPIO_Registers
group-Avnet 0:478cfd88041f 237 * @{
group-Avnet 0:478cfd88041f 238 */
group-Avnet 0:478cfd88041f 239
group-Avnet 0:478cfd88041f 240 /** @defgroup GPIOx_CONF_Registers
group-Avnet 0:478cfd88041f 241 * @{
group-Avnet 0:478cfd88041f 242 */
group-Avnet 0:478cfd88041f 243
group-Avnet 0:478cfd88041f 244 /**
group-Avnet 0:478cfd88041f 245 * \brief GPIOx registers
group-Avnet 0:478cfd88041f 246 * \code
group-Avnet 0:478cfd88041f 247 * Read Write
group-Avnet 0:478cfd88041f 248 * Default value: 0x03
group-Avnet 0:478cfd88041f 249 * 7:3 GPIO_SELECT[4:0]: Specify the I/O signal.
group-Avnet 0:478cfd88041f 250 * GPIO_SELECT[4:0] | I/O | Signal
group-Avnet 0:478cfd88041f 251 * ------------------------------------------------
group-Avnet 0:478cfd88041f 252 * 0 | Output | nIRQ
group-Avnet 0:478cfd88041f 253 * 0 | Input | TX command
group-Avnet 0:478cfd88041f 254 * 1 | Output | POR inverted
group-Avnet 0:478cfd88041f 255 * 1 | Input | RX command
group-Avnet 0:478cfd88041f 256 * 2 | Output | Wake-Up timer expiration
group-Avnet 0:478cfd88041f 257 * 2 | Input | TX data for direct modulation
group-Avnet 0:478cfd88041f 258 * 3 | Output | Low Battery Detection
group-Avnet 0:478cfd88041f 259 * 3 | Input | Wake-up from external input
group-Avnet 0:478cfd88041f 260 * 4 | Output | TX clock output
group-Avnet 0:478cfd88041f 261 * 5 | Output | TX state
group-Avnet 0:478cfd88041f 262 * 6 | Output | TX FIFO Almost Empty Flag
group-Avnet 0:478cfd88041f 263 * 7 | Output | TX FIFO ALmost Full Flag
group-Avnet 0:478cfd88041f 264 * 8 | Output | RX data output
group-Avnet 0:478cfd88041f 265 * 9 | Output | RX clock output
group-Avnet 0:478cfd88041f 266 * 10 | Output | RX state
group-Avnet 0:478cfd88041f 267 * 11 | Output | RX FIFO Almost Full Flag
group-Avnet 0:478cfd88041f 268 * 12 | Output | RX FIFO Almost Empty Flag
group-Avnet 0:478cfd88041f 269 * 13 | Output | Antenna switch
group-Avnet 0:478cfd88041f 270 * 14 | Output | Valid preamble detected
group-Avnet 0:478cfd88041f 271 * 15 | Output | Sync word detected
group-Avnet 0:478cfd88041f 272 * 16 | Output | RSSI above threshold
group-Avnet 0:478cfd88041f 273 * 17 | Output | MCU clock
group-Avnet 0:478cfd88041f 274 * 18 | Output | TX or RX mode indicator
group-Avnet 0:478cfd88041f 275 * 19 | Output | VDD
group-Avnet 0:478cfd88041f 276 * 20 | Output | GND
group-Avnet 0:478cfd88041f 277 * 21 | Output | External SMPS enable signal
group-Avnet 0:478cfd88041f 278 * 22-31 | Not Used | Not Used
group-Avnet 0:478cfd88041f 279 * 2 Reserved
group-Avnet 0:478cfd88041f 280 * 1:0 GpioMode[1:0]: Specify the mode:
group-Avnet 0:478cfd88041f 281 * GPIO_MODE1 | GPIO_MODE0 | MODE
group-Avnet 0:478cfd88041f 282 * ------------------------------------------------------------
group-Avnet 0:478cfd88041f 283 * 0 | 0 | Analog (valid only for GPIO_0)
group-Avnet 0:478cfd88041f 284 * 0 | 1 | Digital Input
group-Avnet 0:478cfd88041f 285 * 1 | 0 | Digital Output Low Power
group-Avnet 0:478cfd88041f 286 * 1 | 1 | Digital Output High Power
group-Avnet 0:478cfd88041f 287 *
group-Avnet 0:478cfd88041f 288 * Note: The Analog mode is used only for temperature sensor indication. This is available only
group-Avnet 0:478cfd88041f 289 * on GPIO_0 by setting the TS bit in the ANA_FUNC_CONF_0_Register.
group-Avnet 0:478cfd88041f 290 * \endcode
group-Avnet 0:478cfd88041f 291 */
group-Avnet 0:478cfd88041f 292
group-Avnet 0:478cfd88041f 293
group-Avnet 0:478cfd88041f 294 #define GPIO3_CONF_BASE ((uint8_t)0x02) /*!< GPIO_3 register address */
group-Avnet 0:478cfd88041f 295 #define GPIO2_CONF_BASE ((uint8_t)0x03) /*!< GPIO_3 register address */
group-Avnet 0:478cfd88041f 296 #define GPIO1_CONF_BASE ((uint8_t)0x04) /*!< GPIO_3 register address */
group-Avnet 0:478cfd88041f 297 #define GPIO0_CONF_BASE ((uint8_t)0x05) /*!< GPIO_3 register address */
group-Avnet 0:478cfd88041f 298
group-Avnet 0:478cfd88041f 299 #define CONF_GPIO_IN_TX_Command ((uint8_t)0x00) /*!< TX command direct from PIN (rising edge, width min=50ns) */
group-Avnet 0:478cfd88041f 300 #define CONF_GPIO_IN_RX_Command ((uint8_t)0x08) /*!< RX command direct from PIN (rising edge, width min=50ns)*/
group-Avnet 0:478cfd88041f 301 #define CONF_GPIO_IN_TX_Data ((uint8_t)0x10) /*!< TX data input for direct modulation */
group-Avnet 0:478cfd88041f 302 #define CONF_GPIO_IN_WKUP_Ext ((uint8_t)0x18) /*!< Wake up from external input */
group-Avnet 0:478cfd88041f 303
group-Avnet 0:478cfd88041f 304 #define CONF_GPIO_OUT_nIRQ ((uint8_t)0x00) /*!< nIRQ (Interrupt Request, active low) , default configuration after POR */
group-Avnet 0:478cfd88041f 305 #define CONF_GPIO_OUT_POR_Inv ((uint8_t)0x08) /*!< POR inverted (active low) */
group-Avnet 0:478cfd88041f 306 #define CONF_GPIO_OUT_WUT_Exp ((uint8_t)0x10) /*!< Wake-Up Timer expiration: ‘1’ when WUT has expired */
group-Avnet 0:478cfd88041f 307 #define CONF_GPIO_OUT_LBD ((uint8_t)0x18) /*!< Low battery detection: ‘1’ when battery is below threshold setting */
group-Avnet 0:478cfd88041f 308 #define CONF_GPIO_OUT_TX_Data ((uint8_t)0x20) /*!< TX data internal clock output (TX data are sampled on the rising edge of it) */
group-Avnet 0:478cfd88041f 309 #define CONF_GPIO_OUT_TX_State ((uint8_t)0x28) /*!< TX state indication: ‘1’ when Spirit1 is transiting in the TX state */
group-Avnet 0:478cfd88041f 310 #define CONF_GPIO_OUT_TX_FIFO_Almost_Empty ((uint8_t)0x30) /*!< TX FIFO Almost Empty Flag */
group-Avnet 0:478cfd88041f 311 #define CONF_GPIO_OUT_TX_FIFO_Amost_Full ((uint8_t)0x38) /*!< TX FIFO Almost Full Flag */
group-Avnet 0:478cfd88041f 312 #define CONF_GPIO_OUT_RX_Data ((uint8_t)0x40) /*!< RX data output */
group-Avnet 0:478cfd88041f 313 #define CONF_GPIO_OUT_RX_Clock ((uint8_t)0x48) /*!< RX clock output (recovered from received data) */
group-Avnet 0:478cfd88041f 314 #define CONF_GPIO_OUT_RX_State ((uint8_t)0x50) /*!< RX state indication: ‘1’ when Spirit1 is transiting in the RX state */
group-Avnet 0:478cfd88041f 315 #define CONF_GPIO_OUT_RX_FIFO_Almost_Full ((uint8_t)0x58) /*!< RX FIFO Almost Full Flag */
group-Avnet 0:478cfd88041f 316 #define CONF_GPIO_OUT_RX_FIFO_Almost_Empty ((uint8_t)0x60) /*!< RX FIFO Almost Empty Flag */
group-Avnet 0:478cfd88041f 317 #define CONF_GPIO_OUT_Antenna_Switch ((uint8_t)0x68) /*!< Antenna switch used for antenna diversity */
group-Avnet 0:478cfd88041f 318 #define CONF_GPIO_OUT_Valid_Preamble ((uint8_t)0x70) /*!< Valid Preamble Detected Flag */
group-Avnet 0:478cfd88041f 319 #define CONF_GPIO_OUT_Sync_Detected ((uint8_t)0x78) /*!< Sync WordSync Word Detected Flag */
group-Avnet 0:478cfd88041f 320 #define CONF_GPIO_OUT_RSSI_Threshold ((uint8_t)0x80) /*!< CCA Assessment Flag */
group-Avnet 0:478cfd88041f 321 #define CONF_GPIO_OUT_MCU_Clock ((uint8_t)0x88) /*!< MCU Clock */
group-Avnet 0:478cfd88041f 322 #define CONF_GPIO_OUT_TX_RX_Mode ((uint8_t)0x90) /*!< TX or RX mode indicator (to enable an external range extender) */
group-Avnet 0:478cfd88041f 323 #define CONF_GPIO_OUT_VDD ((uint8_t)0x98) /*!< VDD (to emulate an additional GPIO of the MCU, programmable by SPI) */
group-Avnet 0:478cfd88041f 324 #define CONF_GPIO_OUT_GND ((uint8_t)0xA0) /*!< GND (to emulate an additional GPIO of the MCU, programmable by SPI) */
group-Avnet 0:478cfd88041f 325 #define CONF_GPIO_OUT_SMPS_Ext ((uint8_t)0xA8) /*!< External SMPS enable signal (active high) */
group-Avnet 0:478cfd88041f 326
group-Avnet 0:478cfd88041f 327 #define CONF_GPIO_MODE_ANALOG ((uint8_t)0x00) /*!< Analog test BUS on GPIO; used only in test mode (except for temperature sensor) */
group-Avnet 0:478cfd88041f 328 #define CONF_GPIO_MODE_DIG_IN ((uint8_t)0x01) /*!< Digital Input on GPIO */
group-Avnet 0:478cfd88041f 329 #define CONF_GPIO_MODE_DIG_OUTL ((uint8_t)0x02) /*!< Digital Output on GPIO (low current) */
group-Avnet 0:478cfd88041f 330 #define CONF_GPIO_MODE_DIG_OUTH ((uint8_t)0x03) /*!< Digital Output on GPIO (high current) */
group-Avnet 0:478cfd88041f 331
group-Avnet 0:478cfd88041f 332 /**
group-Avnet 0:478cfd88041f 333 * @}
group-Avnet 0:478cfd88041f 334 */
group-Avnet 0:478cfd88041f 335
group-Avnet 0:478cfd88041f 336
group-Avnet 0:478cfd88041f 337 /** @defgroup MCU_CK_CONF_Register
group-Avnet 0:478cfd88041f 338 * @{
group-Avnet 0:478cfd88041f 339 */
group-Avnet 0:478cfd88041f 340
group-Avnet 0:478cfd88041f 341 /**
group-Avnet 0:478cfd88041f 342 * \brief MCU_CK_CONF register
group-Avnet 0:478cfd88041f 343 * \code
group-Avnet 0:478cfd88041f 344 * Read Write
group-Avnet 0:478cfd88041f 345 * Default value: 0x00
group-Avnet 0:478cfd88041f 346 * 7 Reserved.
group-Avnet 0:478cfd88041f 347 * 6:5 CLOCK_TAIL[1:0]: Specifies the number of extra cylces provided before entering in STANDBY state.
group-Avnet 0:478cfd88041f 348 * CLOCK_TAIL1 | CLOCK_TAIL0 | Number of Extra Cycles
group-Avnet 0:478cfd88041f 349 * ------------------------------------------------------------
group-Avnet 0:478cfd88041f 350 * 0 | 0 | 0
group-Avnet 0:478cfd88041f 351 * 0 | 1 | 64
group-Avnet 0:478cfd88041f 352 * 1 | 0 | 256
group-Avnet 0:478cfd88041f 353 * 1 | 1 | 512
group-Avnet 0:478cfd88041f 354 * 4:1 XO_RATIO[3:0]: Specifies the division ratio when XO oscillator is the clock source
group-Avnet 0:478cfd88041f 355 * XO_RATIO[3:0] | Division Ratio
group-Avnet 0:478cfd88041f 356 * -----------------------------------
group-Avnet 0:478cfd88041f 357 * 0 | 1
group-Avnet 0:478cfd88041f 358 * 1 | 2/3
group-Avnet 0:478cfd88041f 359 * 2 | 1/2
group-Avnet 0:478cfd88041f 360 * 3 | 1/3
group-Avnet 0:478cfd88041f 361 * 4 | 1/4
group-Avnet 0:478cfd88041f 362 * 5 | 1/6
group-Avnet 0:478cfd88041f 363 * 6 | 1/8
group-Avnet 0:478cfd88041f 364 * 7 | 1/12
group-Avnet 0:478cfd88041f 365 * 8 | 1/16
group-Avnet 0:478cfd88041f 366 * 9 | 1/24
group-Avnet 0:478cfd88041f 367 * 10 | 1/36
group-Avnet 0:478cfd88041f 368 * 11 | 1/48
group-Avnet 0:478cfd88041f 369 * 12 | 1/64
group-Avnet 0:478cfd88041f 370 * 13 | 1/96
group-Avnet 0:478cfd88041f 371 * 14 | 1/128
group-Avnet 0:478cfd88041f 372 * 15 | 1/256
group-Avnet 0:478cfd88041f 373 * 0 RCO_RATIO: Specifies the divsion ratio when RC oscillator is the clock source
group-Avnet 0:478cfd88041f 374 * 0 - Division Ratio equal to 0
group-Avnet 0:478cfd88041f 375 * 1 - Division Ratio equal to 1/128
group-Avnet 0:478cfd88041f 376 * \endcode
group-Avnet 0:478cfd88041f 377 */
group-Avnet 0:478cfd88041f 378
group-Avnet 0:478cfd88041f 379
group-Avnet 0:478cfd88041f 380 #define MCU_CK_CONF_BASE ((uint8_t)0x06) /*!< MCU Clock Config register address */
group-Avnet 0:478cfd88041f 381
group-Avnet 0:478cfd88041f 382 #define MCU_CK_ENABLE ((uint8_t)0x80) /*!< MCU clock enable bit */
group-Avnet 0:478cfd88041f 383
group-Avnet 0:478cfd88041f 384 #define MCU_CK_CONF_CLOCK_TAIL_0 ((uint8_t)0x00) /*!< 0 extra clock cycles provided to the MCU before switching to STANDBY state */
group-Avnet 0:478cfd88041f 385 #define MCU_CK_CONF_CLOCK_TAIL_64 ((uint8_t)0x20) /*!< 64 extra clock cycles provided to the MCU before switching to STANDBY state */
group-Avnet 0:478cfd88041f 386 #define MCU_CK_CONF_CLOCK_TAIL_256 ((uint8_t)0x40) /*!< 256 extra clock cycles provided to the MCU before switching to STANDBY state */
group-Avnet 0:478cfd88041f 387 #define MCU_CK_CONF_CLOCK_TAIL_512 ((uint8_t)0x60) /*!< 512 extra clock cycles provided to the MCU before switching to STANDBY state */
group-Avnet 0:478cfd88041f 388 #define MCU_CK_CONF_XO_RATIO_1 ((uint8_t)0x00) /*!< XO Clock signal available on the GPIO divided by 1 */
group-Avnet 0:478cfd88041f 389 #define MCU_CK_CONF_XO_RATIO_2_3 ((uint8_t)0x02) /*!< XO Clock signal available on the GPIO divided by 2/3 */
group-Avnet 0:478cfd88041f 390 #define MCU_CK_CONF_XO_RATIO_1_2 ((uint8_t)0x04) /*!< XO Clock signal available on the GPIO divided by 1/2 */
group-Avnet 0:478cfd88041f 391 #define MCU_CK_CONF_XO_RATIO_1_3 ((uint8_t)0x06) /*!< XO Clock signal available on the GPIO divided by 1/3 */
group-Avnet 0:478cfd88041f 392 #define MCU_CK_CONF_XO_RATIO_1_4 ((uint8_t)0x08) /*!< XO Clock signal available on the GPIO divided by 1/4 */
group-Avnet 0:478cfd88041f 393 #define MCU_CK_CONF_XO_RATIO_1_6 ((uint8_t)0x0A) /*!< XO Clock signal available on the GPIO divided by 1/6 */
group-Avnet 0:478cfd88041f 394 #define MCU_CK_CONF_XO_RATIO_1_8 ((uint8_t)0x0C) /*!< XO Clock signal available on the GPIO divided by 1/8 */
group-Avnet 0:478cfd88041f 395 #define MCU_CK_CONF_XO_RATIO_1_12 ((uint8_t)0x0E) /*!< XO Clock signal available on the GPIO divided by 1/12 */
group-Avnet 0:478cfd88041f 396 #define MCU_CK_CONF_XO_RATIO_1_16 ((uint8_t)0x10) /*!< XO Clock signal available on the GPIO divided by 1/16 */
group-Avnet 0:478cfd88041f 397 #define MCU_CK_CONF_XO_RATIO_1_24 ((uint8_t)0x12) /*!< XO Clock signal available on the GPIO divided by 1/24 */
group-Avnet 0:478cfd88041f 398 #define MCU_CK_CONF_XO_RATIO_1_36 ((uint8_t)0x14) /*!< XO Clock signal available on the GPIO divided by 1/36 */
group-Avnet 0:478cfd88041f 399 #define MCU_CK_CONF_XO_RATIO_1_48 ((uint8_t)0x16) /*!< XO Clock signal available on the GPIO divided by 1/48 */
group-Avnet 0:478cfd88041f 400 #define MCU_CK_CONF_XO_RATIO_1_64 ((uint8_t)0x18) /*!< XO Clock signal available on the GPIO divided by 1/64 */
group-Avnet 0:478cfd88041f 401 #define MCU_CK_CONF_XO_RATIO_1_96 ((uint8_t)0x1A) /*!< XO Clock signal available on the GPIO divided by 1/96 */
group-Avnet 0:478cfd88041f 402 #define MCU_CK_CONF_XO_RATIO_1_128 ((uint8_t)0x1C) /*!< XO Clock signal available on the GPIO divided by 1/128 */
group-Avnet 0:478cfd88041f 403 #define MCU_CK_CONF_XO_RATIO_1_192 ((uint8_t)0x1E) /*!< XO Clock signal available on the GPIO divided by 1/196 */
group-Avnet 0:478cfd88041f 404 #define MCU_CK_CONF_RCO_RATIO_1 ((uint8_t)0x00) /*!< RCO Clock signal available on the GPIO divided by 1 */
group-Avnet 0:478cfd88041f 405 #define MCU_CK_CONF_RCO_RATIO_1_128 ((uint8_t)0x01) /*!< RCO Clock signal available on the GPIO divided by 1/128*/
group-Avnet 0:478cfd88041f 406
group-Avnet 0:478cfd88041f 407 /**
group-Avnet 0:478cfd88041f 408 * @}
group-Avnet 0:478cfd88041f 409 */
group-Avnet 0:478cfd88041f 410
group-Avnet 0:478cfd88041f 411 /**
group-Avnet 0:478cfd88041f 412 * @}
group-Avnet 0:478cfd88041f 413 */
group-Avnet 0:478cfd88041f 414
group-Avnet 0:478cfd88041f 415
group-Avnet 0:478cfd88041f 416 /** @defgroup Radio_Configuration_Registers
group-Avnet 0:478cfd88041f 417 * @{
group-Avnet 0:478cfd88041f 418 */
group-Avnet 0:478cfd88041f 419
group-Avnet 0:478cfd88041f 420
group-Avnet 0:478cfd88041f 421
group-Avnet 0:478cfd88041f 422 /** @defgroup SYNT3_Register
group-Avnet 0:478cfd88041f 423 * @{
group-Avnet 0:478cfd88041f 424 */
group-Avnet 0:478cfd88041f 425
group-Avnet 0:478cfd88041f 426 /**
group-Avnet 0:478cfd88041f 427 * \brief SYNT3 register
group-Avnet 0:478cfd88041f 428 * \code
group-Avnet 0:478cfd88041f 429 * Read Write
group-Avnet 0:478cfd88041f 430 * Default value: 0x0C
group-Avnet 0:478cfd88041f 431 *
group-Avnet 0:478cfd88041f 432 * 7:5 WCP[2:0]: Set the charge pump current according to the VCO frequency in RX mode.
group-Avnet 0:478cfd88041f 433 *
group-Avnet 0:478cfd88041f 434 * VCO Frequency | WCP2 | WCP1 | WCP0 | Charge Pump Current (uA)
group-Avnet 0:478cfd88041f 435 * ------------------------------------------------------------------------------------------------------------
group-Avnet 0:478cfd88041f 436 * 4644-4678 | 0 | 0 | 0 | 378.4
group-Avnet 0:478cfd88041f 437 * 4708-4772 | 0 | 0 | 1 | 368.9
group-Avnet 0:478cfd88041f 438 * 4772-4836 | 0 | 1 | 0 | 359.5
group-Avnet 0:478cfd88041f 439 * 4836-4902 | 0 | 1 | 1 | 350
group-Avnet 0:478cfd88041f 440 * 4902-4966 | 1 | 0 | 0 | 340.5
group-Avnet 0:478cfd88041f 441 * 4966-5030 | 1 | 0 | 1 | 331.1
group-Avnet 0:478cfd88041f 442 * 5030-5095 | 1 | 1 | 0 | 321.6
group-Avnet 0:478cfd88041f 443 * 5095-5161 | 1 | 1 | 1 | 312.2
group-Avnet 0:478cfd88041f 444 * 5161-5232 | 0 | 0 | 0 | 378.4
group-Avnet 0:478cfd88041f 445 * 5232-5303 | 0 | 0 | 1 | 368.9
group-Avnet 0:478cfd88041f 446 * 5303-5375 | 0 | 1 | 0 | 359.5
group-Avnet 0:478cfd88041f 447 * 5375-5448 | 0 | 1 | 1 | 350
group-Avnet 0:478cfd88041f 448 * 5448-5519 | 1 | 0 | 0 | 340.5
group-Avnet 0:478cfd88041f 449 * 5519-5592 | 1 | 0 | 1 | 331.1
group-Avnet 0:478cfd88041f 450 * 5592-5663 | 1 | 1 | 0 | 321.6
group-Avnet 0:478cfd88041f 451 * 5663-5736 | 1 | 1 | 1 | 312.2
group-Avnet 0:478cfd88041f 452 *
group-Avnet 0:478cfd88041f 453 *
group-Avnet 0:478cfd88041f 454 * 4:0 SYNT[25:21]: highest 5 bits of the PLL programmable divider
group-Avnet 0:478cfd88041f 455 * The valid range depends on fXO and REFDIV settings; for
group-Avnet 0:478cfd88041f 456 * fXO=26MHz
group-Avnet 0:478cfd88041f 457 * REFDIV = 0 - SYNT[25:21] = 11...13
group-Avnet 0:478cfd88041f 458 * REFDIV = 1 - SYNT[25:21] = 22…27
group-Avnet 0:478cfd88041f 459 *
group-Avnet 0:478cfd88041f 460 *
group-Avnet 0:478cfd88041f 461 * \endcode
group-Avnet 0:478cfd88041f 462 */
group-Avnet 0:478cfd88041f 463 #define SYNT3_BASE ((uint8_t)0x08) /*!< [4:0] -> SYNT[25:21], highest 5 bits of the PLL programmable divider */
group-Avnet 0:478cfd88041f 464
group-Avnet 0:478cfd88041f 465 #define WCP_CONF_WCP_378UA ((uint8_t)0x00) /*!< Charge pump current nominal value = 378uA [VCO 4644-4708]&[VCO 5161-5232] */
group-Avnet 0:478cfd88041f 466 #define WCP_CONF_WCP_369UA ((uint8_t)0x01) /*!< Charge pump current nominal value = 369uA [VCO 4708-4772]&[VCO 5232-5303] */
group-Avnet 0:478cfd88041f 467 #define WCP_CONF_WCP_359UA ((uint8_t)0x02) /*!< Charge pump current nominal value = 359uA [VCO 4772-4836]&[VCO 5303-5375] */
group-Avnet 0:478cfd88041f 468 #define WCP_CONF_WCP_350UA ((uint8_t)0x03) /*!< Charge pump current nominal value = 350uA [VCO 4836-4902]&[VCO 5375-5448] */
group-Avnet 0:478cfd88041f 469 #define WCP_CONF_WCP_340UA ((uint8_t)0x04) /*!< Charge pump current nominal value = 340uA [VCO 4902-4966]&[VCO 5448-5519] */
group-Avnet 0:478cfd88041f 470 #define WCP_CONF_WCP_331UA ((uint8_t)0x05) /*!< Charge pump current nominal value = 331uA [VCO 4966-5030]&[VCO 5519-5592] */
group-Avnet 0:478cfd88041f 471 #define WCP_CONF_WCP_321UA ((uint8_t)0x06) /*!< Charge pump current nominal value = 321uA [VCO 5030-5095]&[VCO 5592-5563] */
group-Avnet 0:478cfd88041f 472 #define WCP_CONF_WCP_312UA ((uint8_t)0x07) /*!< Charge pump current nominal value = 312uA [VCO 5095-5160]&[VCO 5563-5736] */
group-Avnet 0:478cfd88041f 473
group-Avnet 0:478cfd88041f 474
group-Avnet 0:478cfd88041f 475 /**
group-Avnet 0:478cfd88041f 476 * @}
group-Avnet 0:478cfd88041f 477 */
group-Avnet 0:478cfd88041f 478
group-Avnet 0:478cfd88041f 479
group-Avnet 0:478cfd88041f 480 /** @defgroup SYNT2_Register
group-Avnet 0:478cfd88041f 481 * @{
group-Avnet 0:478cfd88041f 482 */
group-Avnet 0:478cfd88041f 483
group-Avnet 0:478cfd88041f 484 /**
group-Avnet 0:478cfd88041f 485 * \brief SYNT2 register
group-Avnet 0:478cfd88041f 486 * \code
group-Avnet 0:478cfd88041f 487 * Read Write
group-Avnet 0:478cfd88041f 488 * Default value: 0x84
group-Avnet 0:478cfd88041f 489 * 7:0 SYNT[20:13]: intermediate bits of the PLL programmable divider.
group-Avnet 0:478cfd88041f 490 *
group-Avnet 0:478cfd88041f 491 * \endcode
group-Avnet 0:478cfd88041f 492 */
group-Avnet 0:478cfd88041f 493
group-Avnet 0:478cfd88041f 494 #define SYNT2_BASE ((uint8_t)0x09) /*!< SYNT[20:13], intermediate bits of the PLL programmable divider */
group-Avnet 0:478cfd88041f 495
group-Avnet 0:478cfd88041f 496 /**
group-Avnet 0:478cfd88041f 497 * @}
group-Avnet 0:478cfd88041f 498 */
group-Avnet 0:478cfd88041f 499
group-Avnet 0:478cfd88041f 500 /** @defgroup SYNT1_Register
group-Avnet 0:478cfd88041f 501 * @{
group-Avnet 0:478cfd88041f 502 */
group-Avnet 0:478cfd88041f 503
group-Avnet 0:478cfd88041f 504 /**
group-Avnet 0:478cfd88041f 505 * \brief SYNT1 register
group-Avnet 0:478cfd88041f 506 * \code
group-Avnet 0:478cfd88041f 507 * Read Write
group-Avnet 0:478cfd88041f 508 * Default value: 0xEC
group-Avnet 0:478cfd88041f 509 * 7:0 SYNT[12:5]: intermediate bits of the PLL programmable divider.
group-Avnet 0:478cfd88041f 510 *
group-Avnet 0:478cfd88041f 511 * \endcode
group-Avnet 0:478cfd88041f 512 */
group-Avnet 0:478cfd88041f 513
group-Avnet 0:478cfd88041f 514 #define SYNT1_BASE ((uint8_t)0x0A) /*!< SYNT[12:5], intermediate bits of the PLL programmable divider */
group-Avnet 0:478cfd88041f 515
group-Avnet 0:478cfd88041f 516 /**
group-Avnet 0:478cfd88041f 517 * @}
group-Avnet 0:478cfd88041f 518 */
group-Avnet 0:478cfd88041f 519
group-Avnet 0:478cfd88041f 520 /** @defgroup SYNT0_Register
group-Avnet 0:478cfd88041f 521 * @{
group-Avnet 0:478cfd88041f 522 */
group-Avnet 0:478cfd88041f 523
group-Avnet 0:478cfd88041f 524 /**
group-Avnet 0:478cfd88041f 525 * \brief SYNT0 register
group-Avnet 0:478cfd88041f 526 * \code
group-Avnet 0:478cfd88041f 527 * Read Write
group-Avnet 0:478cfd88041f 528 * Default value: 0x51
group-Avnet 0:478cfd88041f 529 * 7:3 SYNT[4:0]: lowest bits of the PLL programmable divider.
group-Avnet 0:478cfd88041f 530 * 2:0 BS[2:0]: Synthesizer band select. This parameter selects the out-of-loop divide factor of the synthesizer
group-Avnet 0:478cfd88041f 531 * according to the formula fxo/(B/2)/D*SYNT/2^18
group-Avnet 0:478cfd88041f 532 *
group-Avnet 0:478cfd88041f 533 * BS2 | BS1 | BS0 | value of B
group-Avnet 0:478cfd88041f 534 * ---------------------------------------------------------------------------
group-Avnet 0:478cfd88041f 535 * 0 | 0 | 1 | 6
group-Avnet 0:478cfd88041f 536 * 0 | 1 | 0 | 8
group-Avnet 0:478cfd88041f 537 * 0 | 1 | 1 | 12
group-Avnet 0:478cfd88041f 538 * 1 | 0 | 0 | 16
group-Avnet 0:478cfd88041f 539 * 1 | 0 | 1 | 32
group-Avnet 0:478cfd88041f 540 *
group-Avnet 0:478cfd88041f 541 * \endcode
group-Avnet 0:478cfd88041f 542 */
group-Avnet 0:478cfd88041f 543 #define SYNT0_BASE ((uint8_t)0x0B) /*!< [7:3] -> SYNT[4:0], lowest bits of the PLL programmable divider */
group-Avnet 0:478cfd88041f 544
group-Avnet 0:478cfd88041f 545 #define SYNT0_BS_6 ((uint8_t)0x01) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=6 (779-956MHz) */
group-Avnet 0:478cfd88041f 546 #define SYNT0_BS_8 ((uint8_t)0x02) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=8 (387-470MHz)*/
group-Avnet 0:478cfd88041f 547 #define SYNT0_BS_12 ((uint8_t)0x03) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=12 (387-470MHz)*/
group-Avnet 0:478cfd88041f 548 #define SYNT0_BS_16 ((uint8_t)0x04) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=16 (300-348MHz)*/
group-Avnet 0:478cfd88041f 549 #define SYNT0_BS_32 ((uint8_t)0x05) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=32 (150-174MHz)*/
group-Avnet 0:478cfd88041f 550
group-Avnet 0:478cfd88041f 551 /**
group-Avnet 0:478cfd88041f 552 * @}
group-Avnet 0:478cfd88041f 553 */
group-Avnet 0:478cfd88041f 554
group-Avnet 0:478cfd88041f 555 /** @defgroup CHSPACE_Register
group-Avnet 0:478cfd88041f 556 * @{
group-Avnet 0:478cfd88041f 557 */
group-Avnet 0:478cfd88041f 558
group-Avnet 0:478cfd88041f 559 /**
group-Avnet 0:478cfd88041f 560 * \brief CHSPACE register
group-Avnet 0:478cfd88041f 561 * \code
group-Avnet 0:478cfd88041f 562 * Read Write
group-Avnet 0:478cfd88041f 563 * Default value: 0xFC
group-Avnet 0:478cfd88041f 564 * 7:0 CH_SPACING[7:0]: Channel spacing. From ~793Hz to ~200KHz in 793Hz steps
group-Avnet 0:478cfd88041f 565 * (in general, frequency step is fXO/215=26MHz/215~793Hz).
group-Avnet 0:478cfd88041f 566 *
group-Avnet 0:478cfd88041f 567 * \endcode
group-Avnet 0:478cfd88041f 568 */
group-Avnet 0:478cfd88041f 569
group-Avnet 0:478cfd88041f 570 #define CHSPACE_BASE ((uint8_t)0x0C) /*!< Channel spacing. From ~0.8KHz to ~200KHz in (fXO/2^15)Hz (793Hz for 26MHz XO) steps */
group-Avnet 0:478cfd88041f 571
group-Avnet 0:478cfd88041f 572 /**
group-Avnet 0:478cfd88041f 573 * @}
group-Avnet 0:478cfd88041f 574 */
group-Avnet 0:478cfd88041f 575
group-Avnet 0:478cfd88041f 576
group-Avnet 0:478cfd88041f 577
group-Avnet 0:478cfd88041f 578 /** @defgroup IF_OFFSET_DIG_Register
group-Avnet 0:478cfd88041f 579 * @{
group-Avnet 0:478cfd88041f 580 */
group-Avnet 0:478cfd88041f 581
group-Avnet 0:478cfd88041f 582 /**
group-Avnet 0:478cfd88041f 583 * \brief IF_OFFSET_DIG register
group-Avnet 0:478cfd88041f 584 * \code
group-Avnet 0:478cfd88041f 585 * Read Write
group-Avnet 0:478cfd88041f 586 * Default value: 0xA3
group-Avnet 0:478cfd88041f 587 * 7:0 IF_OFFSET_DIG[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz.
group-Avnet 0:478cfd88041f 588 *
group-Avnet 0:478cfd88041f 589 * \endcode
group-Avnet 0:478cfd88041f 590 */
group-Avnet 0:478cfd88041f 591 #define IF_OFFSET_DIG_BASE ((uint8_t)0x0D) /*!< Intermediate frequency fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz */
group-Avnet 0:478cfd88041f 592
group-Avnet 0:478cfd88041f 593 /**
group-Avnet 0:478cfd88041f 594 * @}
group-Avnet 0:478cfd88041f 595 */
group-Avnet 0:478cfd88041f 596
group-Avnet 0:478cfd88041f 597 /** @defgroup IF_OFFSET_ANA_Register
group-Avnet 0:478cfd88041f 598 * @{
group-Avnet 0:478cfd88041f 599 */
group-Avnet 0:478cfd88041f 600
group-Avnet 0:478cfd88041f 601 /**
group-Avnet 0:478cfd88041f 602 * \brief IF_OFFSET_ANA register
group-Avnet 0:478cfd88041f 603 * \code
group-Avnet 0:478cfd88041f 604 * Read Write
group-Avnet 0:478cfd88041f 605 * Default value: 0xA3
group-Avnet 0:478cfd88041f 606 * 7:0 IF_OFFSET_ANA[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz.
group-Avnet 0:478cfd88041f 607 *
group-Avnet 0:478cfd88041f 608 * \endcode
group-Avnet 0:478cfd88041f 609 */
group-Avnet 0:478cfd88041f 610 #define IF_OFFSET_ANA_BASE ((uint8_t)0x07) /*!< Intermediate frequency fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz */
group-Avnet 0:478cfd88041f 611
group-Avnet 0:478cfd88041f 612
group-Avnet 0:478cfd88041f 613 /**
group-Avnet 0:478cfd88041f 614 * @}
group-Avnet 0:478cfd88041f 615 */
group-Avnet 0:478cfd88041f 616
group-Avnet 0:478cfd88041f 617 /** @defgroup FC_OFFSET1_Register
group-Avnet 0:478cfd88041f 618 * @{
group-Avnet 0:478cfd88041f 619 */
group-Avnet 0:478cfd88041f 620
group-Avnet 0:478cfd88041f 621 /**
group-Avnet 0:478cfd88041f 622 * \brief FC_OFFSET1 registers
group-Avnet 0:478cfd88041f 623 * \code
group-Avnet 0:478cfd88041f 624 * Read Write
group-Avnet 0:478cfd88041f 625 * Default value: 0xA3
group-Avnet 0:478cfd88041f 626 * 7:4 Reserved.
group-Avnet 0:478cfd88041f 627 * 3:0 FC_OFFSET[11:8]: Carrier offset. This value is the higher part of a 12-bit 2’s complement integer
group-Avnet 0:478cfd88041f 628 * representing an offset in 99Hz(2) units added/subtracted to the
group-Avnet 0:478cfd88041f 629 * carrier frequency set by registers SYNT3…SYNT0.
group-Avnet 0:478cfd88041f 630 * This register can be used to set a fixed correction value
group-Avnet 0:478cfd88041f 631 * obtained e.g. from crystal measurements.
group-Avnet 0:478cfd88041f 632 *
group-Avnet 0:478cfd88041f 633 * \endcode
group-Avnet 0:478cfd88041f 634 */
group-Avnet 0:478cfd88041f 635 #define FC_OFFSET1_BASE ((uint8_t)0x0E) /*!< [3:0] -> [11:8] Carrier offset (upper part) */
group-Avnet 0:478cfd88041f 636
group-Avnet 0:478cfd88041f 637 /**
group-Avnet 0:478cfd88041f 638 * @}
group-Avnet 0:478cfd88041f 639 */
group-Avnet 0:478cfd88041f 640
group-Avnet 0:478cfd88041f 641
group-Avnet 0:478cfd88041f 642 /** @defgroup FC_OFFSET0_Register
group-Avnet 0:478cfd88041f 643 * @{
group-Avnet 0:478cfd88041f 644 */
group-Avnet 0:478cfd88041f 645
group-Avnet 0:478cfd88041f 646 /**
group-Avnet 0:478cfd88041f 647 * \brief FC_OFFSET0 registers
group-Avnet 0:478cfd88041f 648 * \code
group-Avnet 0:478cfd88041f 649 * Default value: 0x00
group-Avnet 0:478cfd88041f 650 * Read Write
group-Avnet 0:478cfd88041f 651 * 7:0 FC_OFFSET[7:0]: Carrier offset. This value is the lower part of a 12-bit 2’s complement integer
group-Avnet 0:478cfd88041f 652 * representing an offset in 99Hz(2) units added/subtracted to the
group-Avnet 0:478cfd88041f 653 * carrier frequency set by registers SYNT3…SYNT0.
group-Avnet 0:478cfd88041f 654 * This register can be used to set a fixed correction value
group-Avnet 0:478cfd88041f 655 * obtained e.g. from crystal measurements.
group-Avnet 0:478cfd88041f 656 *
group-Avnet 0:478cfd88041f 657 * \endcode
group-Avnet 0:478cfd88041f 658 */
group-Avnet 0:478cfd88041f 659 #define FC_OFFSET0_BASE ((uint8_t)0x0F) /*!< [7:0] -> [7:0] Carrier offset (lower part). This value is a 12-bit 2’s complement integer
group-Avnet 0:478cfd88041f 660 representing an offset in fXO/2^18 (99Hz for 26 MHz XO) units added/subtracted to the carrier frequency
group-Avnet 0:478cfd88041f 661 set by registers SYNT3…SYNT0. Range is +/-200kHz with 26 MHz XO */
group-Avnet 0:478cfd88041f 662 /**
group-Avnet 0:478cfd88041f 663 * @}
group-Avnet 0:478cfd88041f 664 */
group-Avnet 0:478cfd88041f 665
group-Avnet 0:478cfd88041f 666
group-Avnet 0:478cfd88041f 667 /** @defgroup PA_LEVEL_x_Registers
group-Avnet 0:478cfd88041f 668 * @{
group-Avnet 0:478cfd88041f 669 */
group-Avnet 0:478cfd88041f 670
group-Avnet 0:478cfd88041f 671 /**
group-Avnet 0:478cfd88041f 672 * \brief PA_POWER_x[8:1] registers
group-Avnet 0:478cfd88041f 673 * \code
group-Avnet 0:478cfd88041f 674 * Default values from 8 to 1: [0x03, 0x0E, 0x1A, 0x25, 0x35, 0x40, 0x4E, 0x00]
group-Avnet 0:478cfd88041f 675 * Read Write
group-Avnet 0:478cfd88041f 676 *
group-Avnet 0:478cfd88041f 677 * 7 Reserved.
group-Avnet 0:478cfd88041f 678 * 6:0 PA_LEVEL_(x-1)[6:0]: Output power level for x-th slot.
group-Avnet 0:478cfd88041f 679 * \endcode
group-Avnet 0:478cfd88041f 680 */
group-Avnet 0:478cfd88041f 681
group-Avnet 0:478cfd88041f 682 #define PA_POWER8_BASE ((uint8_t)0x10) /*!< PA Power level for 8th slot of PA ramping or ASK modulation */
group-Avnet 0:478cfd88041f 683 #define PA_POWER7_BASE ((uint8_t)0x11) /*!< PA Power level for 7th slot of PA ramping or ASK modulation */
group-Avnet 0:478cfd88041f 684 #define PA_POWER6_BASE ((uint8_t)0x12) /*!< PA Power level for 6th slot of PA ramping or ASK modulation */
group-Avnet 0:478cfd88041f 685 #define PA_POWER5_BASE ((uint8_t)0x13) /*!< PA Power level for 5th slot of PA ramping or ASK modulation */
group-Avnet 0:478cfd88041f 686 #define PA_POWER4_BASE ((uint8_t)0x14) /*!< PA Power level for 4th slot of PA ramping or ASK modulation */
group-Avnet 0:478cfd88041f 687 #define PA_POWER3_BASE ((uint8_t)0x15) /*!< PA Power level for 3rd slot of PA ramping or ASK modulation */
group-Avnet 0:478cfd88041f 688 #define PA_POWER2_BASE ((uint8_t)0x16) /*!< PA Power level for 2nd slot of PA ramping or ASK modulation */
group-Avnet 0:478cfd88041f 689 #define PA_POWER1_BASE ((uint8_t)0x17) /*!< PA Power level for 1st slot of PA ramping or ASK modulation */
group-Avnet 0:478cfd88041f 690
group-Avnet 0:478cfd88041f 691 /**
group-Avnet 0:478cfd88041f 692 * @}
group-Avnet 0:478cfd88041f 693 */
group-Avnet 0:478cfd88041f 694
group-Avnet 0:478cfd88041f 695 /** @defgroup PA_POWER_CONF_Registers
group-Avnet 0:478cfd88041f 696 * @{
group-Avnet 0:478cfd88041f 697 */
group-Avnet 0:478cfd88041f 698
group-Avnet 0:478cfd88041f 699 /**
group-Avnet 0:478cfd88041f 700 * \brief PA_POWER_CONF_Registers
group-Avnet 0:478cfd88041f 701 * \code
group-Avnet 0:478cfd88041f 702 * Default value:0x07
group-Avnet 0:478cfd88041f 703 * Read Write
group-Avnet 0:478cfd88041f 704 *
group-Avnet 0:478cfd88041f 705 * 7:6 CWC[1:0]: Output stage additional load capacitors bank (to be used to
group-Avnet 0:478cfd88041f 706 * optimize the PA for different sub-bands).
group-Avnet 0:478cfd88041f 707 *
group-Avnet 0:478cfd88041f 708 * CWC1 | CWC0 | Total capacity in pF
group-Avnet 0:478cfd88041f 709 * ---------------------------------------------------------
group-Avnet 0:478cfd88041f 710 * 0 | 0 | 0
group-Avnet 0:478cfd88041f 711 * 0 | 1 | 1.2
group-Avnet 0:478cfd88041f 712 * 1 | 0 | 2.4
group-Avnet 0:478cfd88041f 713 * 1 | 1 | 3.6
group-Avnet 0:478cfd88041f 714 *
group-Avnet 0:478cfd88041f 715 * 5 PA_RAMP_ENABLE:
group-Avnet 0:478cfd88041f 716 * 1 - Enable the power ramping
group-Avnet 0:478cfd88041f 717 * 0 - Disable the power ramping
group-Avnet 0:478cfd88041f 718 * 4:3 PA_RAMP_STEP_WIDTH[1:0]: Step width in bit period
group-Avnet 0:478cfd88041f 719 *
group-Avnet 0:478cfd88041f 720 * PA_RAMP_STEP_WIDTH1 | PA_RAMP_STEP_WIDTH0 | PA ramping time step
group-Avnet 0:478cfd88041f 721 * -------------------------------------------------------------------------------------------
group-Avnet 0:478cfd88041f 722 * 0 | 0 | 1/8 Bit period
group-Avnet 0:478cfd88041f 723 * 0 | 1 | 2/8 Bit period
group-Avnet 0:478cfd88041f 724 * 1 | 0 | 3/8 Bit period
group-Avnet 0:478cfd88041f 725 * 1 | 1 | 4/8 Bit period
group-Avnet 0:478cfd88041f 726 *
group-Avnet 0:478cfd88041f 727 * 2:0 PA_LEVEL_MAX_INDEX[2:0]: Fixes the MAX PA LEVEL in PA ramping or ASK modulation
group-Avnet 0:478cfd88041f 728 *
group-Avnet 0:478cfd88041f 729 * \endcode
group-Avnet 0:478cfd88041f 730 */
group-Avnet 0:478cfd88041f 731 #define PA_POWER0_BASE ((uint8_t)0x18) /*!< PA ramping settings and additional load capacitor banks used
group-Avnet 0:478cfd88041f 732 for PA optimization in different sub bands*/
group-Avnet 0:478cfd88041f 733 #define PA_POWER0_CWC_MASK ((uint8_t)0x20) /*!< Output stage additional load capacitors bank */
group-Avnet 0:478cfd88041f 734 #define PA_POWER0_CWC_0 ((uint8_t)0x00) /*!< No additional PA load capacitor */
group-Avnet 0:478cfd88041f 735 #define PA_POWER0_CWC_1_2P ((uint8_t)0x40) /*!< 1.2pF additional PA load capacitor */
group-Avnet 0:478cfd88041f 736 #define PA_POWER0_CWC_2_4P ((uint8_t)0x80) /*!< 2.4pF additional PA load capacitor */
group-Avnet 0:478cfd88041f 737 #define PA_POWER0_CWC_3_6P ((uint8_t)0xC0) /*!< 3.6pF additional PA load capacitor */
group-Avnet 0:478cfd88041f 738 #define PA_POWER0_PA_RAMP_MASK ((uint8_t)0x20) /*!< The PA power ramping */
group-Avnet 0:478cfd88041f 739 #define PA_POWER0_PA_RAMP_STEP_WIDTH_MASK ((uint8_t)0x20) /*!< The step width */
group-Avnet 0:478cfd88041f 740 #define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_8 ((uint8_t)0x00) /*!< PA ramping time step = 1/8 Bit period*/
group-Avnet 0:478cfd88041f 741 #define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_4 ((uint8_t)0x08) /*!< PA ramping time step = 2/8 Bit period*/
group-Avnet 0:478cfd88041f 742 #define PA_POWER0_PA_RAMP_STEP_WIDTH_3TB_8 ((uint8_t)0x10) /*!< PA ramping time step = 3/8 Bit period*/
group-Avnet 0:478cfd88041f 743 #define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_2 ((uint8_t)0x18) /*!< PA ramping time step = 4/8 Bit period*/
group-Avnet 0:478cfd88041f 744 #define PA_POWER0_PA_LEVEL_MAX_INDEX ((uint8_t)0x20) /*!< Final level for power ramping */
group-Avnet 0:478cfd88041f 745 #define PA_POWER0_PA_LEVEL_MAX_INDEX_0 ((uint8_t)0x00) /*!< */
group-Avnet 0:478cfd88041f 746 #define PA_POWER0_PA_LEVEL_MAX_INDEX_1 ((uint8_t)0x01) /*!< Fixes the MAX PA LEVEL in PA ramping or ASK modulation */
group-Avnet 0:478cfd88041f 747 #define PA_POWER0_PA_LEVEL_MAX_INDEX_2 ((uint8_t)0x02) /*!< */
group-Avnet 0:478cfd88041f 748 #define PA_POWER0_PA_LEVEL_MAX_INDEX_3 ((uint8_t)0x03) /*!< _________ */
group-Avnet 0:478cfd88041f 749 #define PA_POWER0_PA_LEVEL_MAX_INDEX_4 ((uint8_t)0x04) /*!< PA_LVL2 _| <--| */
group-Avnet 0:478cfd88041f 750 #define PA_POWER0_PA_LEVEL_MAX_INDEX_5 ((uint8_t)0x05) /*!< _| | */
group-Avnet 0:478cfd88041f 751 #define PA_POWER0_PA_LEVEL_MAX_INDEX_6 ((uint8_t)0x06) /*!< PA_LVL1 _| | */
group-Avnet 0:478cfd88041f 752 #define PA_POWER0_PA_LEVEL_MAX_INDEX_7 ((uint8_t)0x07) /*!< PA_LVL0 _| MAX_INDEX- */
group-Avnet 0:478cfd88041f 753
group-Avnet 0:478cfd88041f 754
group-Avnet 0:478cfd88041f 755
group-Avnet 0:478cfd88041f 756 /**
group-Avnet 0:478cfd88041f 757 * @}
group-Avnet 0:478cfd88041f 758 */
group-Avnet 0:478cfd88041f 759
group-Avnet 0:478cfd88041f 760
group-Avnet 0:478cfd88041f 761 /** @defgroup MOD1_Register
group-Avnet 0:478cfd88041f 762 * @{
group-Avnet 0:478cfd88041f 763 */
group-Avnet 0:478cfd88041f 764
group-Avnet 0:478cfd88041f 765 /**
group-Avnet 0:478cfd88041f 766 * \brief MOD1 register
group-Avnet 0:478cfd88041f 767 * \code
group-Avnet 0:478cfd88041f 768 * Read Write
group-Avnet 0:478cfd88041f 769 * Default value: 0x83
group-Avnet 0:478cfd88041f 770 * 7:0 DATARATE_M[7:0]: The Mantissa of the specified data rate
group-Avnet 0:478cfd88041f 771 *
group-Avnet 0:478cfd88041f 772 * \endcode
group-Avnet 0:478cfd88041f 773 */
group-Avnet 0:478cfd88041f 774 #define MOD1_BASE ((uint8_t)0x1A) /*!< The Mantissa of the specified data rate */
group-Avnet 0:478cfd88041f 775
group-Avnet 0:478cfd88041f 776 /**
group-Avnet 0:478cfd88041f 777 * @}
group-Avnet 0:478cfd88041f 778 */
group-Avnet 0:478cfd88041f 779
group-Avnet 0:478cfd88041f 780 /** @defgroup MOD0_Register
group-Avnet 0:478cfd88041f 781 * @{
group-Avnet 0:478cfd88041f 782 */
group-Avnet 0:478cfd88041f 783
group-Avnet 0:478cfd88041f 784 /**
group-Avnet 0:478cfd88041f 785 * \brief MOD0 register
group-Avnet 0:478cfd88041f 786 * \code
group-Avnet 0:478cfd88041f 787 * Read Write
group-Avnet 0:478cfd88041f 788 * Default value: 0x1A
group-Avnet 0:478cfd88041f 789 * 7 CW: 1 - CW Mode enabled - enables the generation of a continous wave carrier without any modulation
group-Avnet 0:478cfd88041f 790 * 0 - CW Mode disabled
group-Avnet 0:478cfd88041f 791 *
group-Avnet 0:478cfd88041f 792 * 6 BT_SEL: Select BT value for GFSK
group-Avnet 0:478cfd88041f 793 * 1 - BT=0.5
group-Avnet 0:478cfd88041f 794 * 0 - BT=1
group-Avnet 0:478cfd88041f 795 *
group-Avnet 0:478cfd88041f 796 * 5:4 MOD_TYPE[1:0]: Modulation type
group-Avnet 0:478cfd88041f 797 *
group-Avnet 0:478cfd88041f 798 *
group-Avnet 0:478cfd88041f 799 * MOD_TYPE1 | MOD_TYPE0 | Modulation
group-Avnet 0:478cfd88041f 800 * ---------------------------------------------------------
group-Avnet 0:478cfd88041f 801 * 0 | 0 | 2-FSK,MSK
group-Avnet 0:478cfd88041f 802 * 0 | 1 | GFSK,GMSK
group-Avnet 0:478cfd88041f 803 * 1 | 0 | ASK/OOK
group-Avnet 0:478cfd88041f 804 *
group-Avnet 0:478cfd88041f 805 * 3:0 DATARATE_E[3:0]: The Exponent of the specified data rate
group-Avnet 0:478cfd88041f 806 *
group-Avnet 0:478cfd88041f 807 * \endcode
group-Avnet 0:478cfd88041f 808 */
group-Avnet 0:478cfd88041f 809 #define MOD0_BASE ((uint8_t)0x1B) /*!< Modulation Settings, Exponent of the specified data rate, CW mode*/
group-Avnet 0:478cfd88041f 810
group-Avnet 0:478cfd88041f 811 #define MOD0_MOD_TYPE_2_FSK ((uint8_t)0x00) /*!< Modulation type 2-FSK (MSK if the frequency deviation is identical to a quarter of the data rate) */
group-Avnet 0:478cfd88041f 812 #define MOD0_MOD_TYPE_GFSK ((uint8_t)0x10) /*!< Modulation type GFSK (GMSK if the frequency deviation is identical to a quarter of the data rate) */
group-Avnet 0:478cfd88041f 813 #define MOD0_MOD_TYPE_ASK ((uint8_t)0x20) /*!< Modulation type ASK (OOK the PA is switched off for symbol "0") */
group-Avnet 0:478cfd88041f 814 #define MOD0_MOD_TYPE_MSK ((uint8_t)0x00) /*!< Modulation type MSK (the frequency deviation must be identical to a quarter of the data rate) */
group-Avnet 0:478cfd88041f 815 #define MOD0_MOD_TYPE_GMSK ((uint8_t)0x10) /*!< Modulation type GMSK (the frequency deviation must be identical to a quarter of the data rate) */
group-Avnet 0:478cfd88041f 816 #define MOD0_BT_SEL_BT_MASK ((uint8_t)0x00) /*!< Select the BT = 1 or BT = 0.5 valid only for GFSK or GMSK modulation*/
group-Avnet 0:478cfd88041f 817 #define MOD0_CW ((uint8_t)0x80) /*!< Set the Continous Wave (no modulation) transmit mode */
group-Avnet 0:478cfd88041f 818
group-Avnet 0:478cfd88041f 819 /**
group-Avnet 0:478cfd88041f 820 * @}
group-Avnet 0:478cfd88041f 821 */
group-Avnet 0:478cfd88041f 822
group-Avnet 0:478cfd88041f 823
group-Avnet 0:478cfd88041f 824 /** @defgroup FDEV0_Register
group-Avnet 0:478cfd88041f 825 * @{
group-Avnet 0:478cfd88041f 826 */
group-Avnet 0:478cfd88041f 827
group-Avnet 0:478cfd88041f 828 /**
group-Avnet 0:478cfd88041f 829 * \brief FDEV0 register
group-Avnet 0:478cfd88041f 830 * \code
group-Avnet 0:478cfd88041f 831 * Read Write
group-Avnet 0:478cfd88041f 832 * Default value: 0x45
group-Avnet 0:478cfd88041f 833 * 7:4 FDEV_E[3:0]: Exponent of the frequency deviation (allowed values from 0 to 9)
group-Avnet 0:478cfd88041f 834 *
group-Avnet 0:478cfd88041f 835 * 3 CLOCK_REC_ALGO_SEL: Select PLL or DLL mode for clock recovery
group-Avnet 0:478cfd88041f 836 * 1 - DLL mode
group-Avnet 0:478cfd88041f 837 * 0 - PLL mode
group-Avnet 0:478cfd88041f 838 *
group-Avnet 0:478cfd88041f 839 * 2:0 FDEV_M[1:0]: Mantissa of the frequency deviation (allowed values from 0 to 7)
group-Avnet 0:478cfd88041f 840 *
group-Avnet 0:478cfd88041f 841 *
group-Avnet 0:478cfd88041f 842 * \endcode
group-Avnet 0:478cfd88041f 843 */
group-Avnet 0:478cfd88041f 844 #define FDEV0_BASE ((uint8_t)0x1C) /*!< Sets the Mantissa and exponent of frequency deviation (frequency separation/2)
group-Avnet 0:478cfd88041f 845 and PLL or DLL alogrithm from clock recovery in RX digital demod*/
group-Avnet 0:478cfd88041f 846 #define FDEV0_CLOCK_REG_ALGO_SEL_MASK ((uint8_t)0x08) /*!< Can be DLL or PLL algorithm for clock recovery in RX digital demod (see CLOCKREC reg) */
group-Avnet 0:478cfd88041f 847 #define FDEV0_CLOCK_REG_ALGO_SEL_PLL ((uint8_t)0x00) /*!< Sets PLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) */
group-Avnet 0:478cfd88041f 848 #define FDEV0_CLOCK_REG_ALGO_SEL_DLL ((uint8_t)0x08) /*!< Sets DLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) */
group-Avnet 0:478cfd88041f 849
group-Avnet 0:478cfd88041f 850 /**
group-Avnet 0:478cfd88041f 851 * @}
group-Avnet 0:478cfd88041f 852 */
group-Avnet 0:478cfd88041f 853
group-Avnet 0:478cfd88041f 854 /** @defgroup CHFLT_Register
group-Avnet 0:478cfd88041f 855 * @{
group-Avnet 0:478cfd88041f 856 */
group-Avnet 0:478cfd88041f 857
group-Avnet 0:478cfd88041f 858 /**
group-Avnet 0:478cfd88041f 859 * \brief CHFLT register
group-Avnet 0:478cfd88041f 860 * \code
group-Avnet 0:478cfd88041f 861 * Read Write
group-Avnet 0:478cfd88041f 862 * Default value: 0x23
group-Avnet 0:478cfd88041f 863 * 7:4 CHFLT_M[3:0]: Mantissa of the channel filter BW (allowed values from 0 to 8)
group-Avnet 0:478cfd88041f 864 *
group-Avnet 0:478cfd88041f 865 * 3:0 CHFLT_E[3:0]: Exponent of the channel filter BW (allowed values from 0 to 9)
group-Avnet 0:478cfd88041f 866 *
group-Avnet 0:478cfd88041f 867 * M\E | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
group-Avnet 0:478cfd88041f 868 * -----+-------+-------+-------+-------+------+------+------+-----+-----+-----+
group-Avnet 0:478cfd88041f 869 * 0 | 800.1 | 450.9 | 224.7 | 112.3 | 56.1 | 28.0 | 14.0 | 7.0 | 3.5 | 1.8 |
group-Avnet 0:478cfd88041f 870 * 1 | 795.1 | 425.9 | 212.4 | 106.2 | 53.0 | 26.5 | 13.3 | 6.6 | 3.3 | 1.7 |
group-Avnet 0:478cfd88041f 871 * 2 | 768.4 | 403.2 | 201.1 | 100.5 | 50.2 | 25.1 | 12.6 | 6.3 | 3.1 | 1.6 |
group-Avnet 0:478cfd88041f 872 * 3 | 736.8 | 380.8 | 190.0 | 95.0 | 47.4 | 23.7 | 11.9 | 5.9 | 3.0 | 1.5 |
group-Avnet 0:478cfd88041f 873 * 4 | 705.1 | 362.1 | 180.7 | 90.3 | 45.1 | 22.6 | 11.3 | 5.6 | 2.8 | 1.4 |
group-Avnet 0:478cfd88041f 874 * 5 | 670.9 | 341.7 | 170.6 | 85.3 | 42.6 | 21.3 | 10.6 | 5.3 | 2.7 | 1.3 |
group-Avnet 0:478cfd88041f 875 * 6 | 642.3 | 325.4 | 162.4 | 81.2 | 40.6 | 20.3 | 10.1 | 5.1 | 2.5 | 1.3 |
group-Avnet 0:478cfd88041f 876 * 7 | 586.7 | 294.5 | 147.1 | 73.5 | 36.7 | 18.4 | 9.2 | 4.6 | 2.3 | 1.2 |
group-Avnet 0:478cfd88041f 877 * 8 | 541.4 | 270.3 | 135.0 | 67.5 | 33.7 | 16.9 | 8.4 | 4.2 | 2.1 | 1.1 |
group-Avnet 0:478cfd88041f 878 *
group-Avnet 0:478cfd88041f 879 * \endcode
group-Avnet 0:478cfd88041f 880 */
group-Avnet 0:478cfd88041f 881 #define CHFLT_BASE ((uint8_t)0x1D) /*!< RX Channel Filter Bandwidth */
group-Avnet 0:478cfd88041f 882
group-Avnet 0:478cfd88041f 883 #define CHFLT_800_1 ((uint8_t)0x00) /*!< RX Channel Filter Bandwidth = 800.1 kHz */
group-Avnet 0:478cfd88041f 884 #define CHFLT_795_1 ((uint8_t)0x10) /*!< RX Channel Filter Bandwidth = 795.1 kHz */
group-Avnet 0:478cfd88041f 885 #define CHFLT_768_4 ((uint8_t)0x20) /*!< RX Channel Filter Bandwidth = 768.4 kHz */
group-Avnet 0:478cfd88041f 886 #define CHFLT_736_8 ((uint8_t)0x30) /*!< RX Channel Filter Bandwidth = 736.8 kHz */
group-Avnet 0:478cfd88041f 887 #define CHFLT_705_1 ((uint8_t)0x40) /*!< RX Channel Filter Bandwidth = 705.1 kHz */
group-Avnet 0:478cfd88041f 888 #define CHFLT_670_9 ((uint8_t)0x50) /*!< RX Channel Filter Bandwidth = 670.9 kHz */
group-Avnet 0:478cfd88041f 889 #define CHFLT_642_3 ((uint8_t)0x60) /*!< RX Channel Filter Bandwidth = 642.3 kHz */
group-Avnet 0:478cfd88041f 890 #define CHFLT_586_7 ((uint8_t)0x70) /*!< RX Channel Filter Bandwidth = 586.7 kHz */
group-Avnet 0:478cfd88041f 891 #define CHFLT_541_4 ((uint8_t)0x80) /*!< RX Channel Filter Bandwidth = 541.4 kHz */
group-Avnet 0:478cfd88041f 892 #define CHFLT_450_9 ((uint8_t)0x01) /*!< RX Channel Filter Bandwidth = 450.9 kHz */
group-Avnet 0:478cfd88041f 893 #define CHFLT_425_9 ((uint8_t)0x11) /*!< RX Channel Filter Bandwidth = 425.9 kHz */
group-Avnet 0:478cfd88041f 894 #define CHFLT_403_2 ((uint8_t)0x21) /*!< RX Channel Filter Bandwidth = 403.2 kHz */
group-Avnet 0:478cfd88041f 895 #define CHFLT_380_8 ((uint8_t)0x31) /*!< RX Channel Filter Bandwidth = 380.8 kHz */
group-Avnet 0:478cfd88041f 896 #define CHFLT_362_1 ((uint8_t)0x41) /*!< RX Channel Filter Bandwidth = 362.1 kHz */
group-Avnet 0:478cfd88041f 897 #define CHFLT_341_7 ((uint8_t)0x51) /*!< RX Channel Filter Bandwidth = 341.7 kHz */
group-Avnet 0:478cfd88041f 898 #define CHFLT_325_4 ((uint8_t)0x61) /*!< RX Channel Filter Bandwidth = 325.4 kHz */
group-Avnet 0:478cfd88041f 899 #define CHFLT_294_5 ((uint8_t)0x71) /*!< RX Channel Filter Bandwidth = 294.5 kHz */
group-Avnet 0:478cfd88041f 900 #define CHFLT_270_3 ((uint8_t)0x81) /*!< RX Channel Filter Bandwidth = 270.3 kHz */
group-Avnet 0:478cfd88041f 901 #define CHFLT_224_7 ((uint8_t)0x02) /*!< RX Channel Filter Bandwidth = 224.7 kHz */
group-Avnet 0:478cfd88041f 902 #define CHFLT_212_4 ((uint8_t)0x12) /*!< RX Channel Filter Bandwidth = 212.4 kHz */
group-Avnet 0:478cfd88041f 903 #define CHFLT_201_1 ((uint8_t)0x22) /*!< RX Channel Filter Bandwidth = 201.1 kHz */
group-Avnet 0:478cfd88041f 904 #define CHFLT_190 ((uint8_t)0x32) /*!< RX Channel Filter Bandwidth = 190.0 kHz */
group-Avnet 0:478cfd88041f 905 #define CHFLT_180_7 ((uint8_t)0x42) /*!< RX Channel Filter Bandwidth = 180.7 kHz */
group-Avnet 0:478cfd88041f 906 #define CHFLT_170_6 ((uint8_t)0x52) /*!< RX Channel Filter Bandwidth = 170.6 kHz */
group-Avnet 0:478cfd88041f 907 #define CHFLT_162_4 ((uint8_t)0x62) /*!< RX Channel Filter Bandwidth = 162.4 kHz */
group-Avnet 0:478cfd88041f 908 #define CHFLT_147_1 ((uint8_t)0x72) /*!< RX Channel Filter Bandwidth = 147.1 kHz */
group-Avnet 0:478cfd88041f 909 #define CHFLT_135 ((uint8_t)0x82) /*!< RX Channel Filter Bandwidth = 135.0 kHz */
group-Avnet 0:478cfd88041f 910 #define CHFLT_112_3 ((uint8_t)0x03) /*!< RX Channel Filter Bandwidth = 112.3 kHz */
group-Avnet 0:478cfd88041f 911 #define CHFLT_106_2 ((uint8_t)0x13) /*!< RX Channel Filter Bandwidth = 106.2 kHz */
group-Avnet 0:478cfd88041f 912 #define CHFLT_100_5 ((uint8_t)0x23) /*!< RX Channel Filter Bandwidth = 100.5 kHz */
group-Avnet 0:478cfd88041f 913 #define CHFLT_95 ((uint8_t)0x33) /*!< RX Channel Filter Bandwidth = 95.0 kHz */
group-Avnet 0:478cfd88041f 914 #define CHFLT_90_3 ((uint8_t)0x43) /*!< RX Channel Filter Bandwidth = 90.3 kHz */
group-Avnet 0:478cfd88041f 915 #define CHFLT_85_3 ((uint8_t)0x53) /*!< RX Channel Filter Bandwidth = 85.3 kHz */
group-Avnet 0:478cfd88041f 916 #define CHFLT_81_2 ((uint8_t)0x63) /*!< RX Channel Filter Bandwidth = 81.2 kHz */
group-Avnet 0:478cfd88041f 917 #define CHFLT_73_5 ((uint8_t)0x73) /*!< RX Channel Filter Bandwidth = 73.5 kHz */
group-Avnet 0:478cfd88041f 918 #define CHFLT_67_5 ((uint8_t)0x83) /*!< RX Channel Filter Bandwidth = 67.5 kHz */
group-Avnet 0:478cfd88041f 919 #define CHFLT_56_1 ((uint8_t)0x04) /*!< RX Channel Filter Bandwidth = 56.1 kHz */
group-Avnet 0:478cfd88041f 920 #define CHFLT_53 ((uint8_t)0x14) /*!< RX Channel Filter Bandwidth = 53.0 kHz */
group-Avnet 0:478cfd88041f 921 #define CHFLT_50_2 ((uint8_t)0x24) /*!< RX Channel Filter Bandwidth = 50.2 kHz */
group-Avnet 0:478cfd88041f 922 #define CHFLT_47_4 ((uint8_t)0x34) /*!< RX Channel Filter Bandwidth = 47.4 kHz */
group-Avnet 0:478cfd88041f 923 #define CHFLT_45_1 ((uint8_t)0x44) /*!< RX Channel Filter Bandwidth = 45.1 kHz */
group-Avnet 0:478cfd88041f 924 #define CHFLT_42_6 ((uint8_t)0x54) /*!< RX Channel Filter Bandwidth = 42.6 kHz */
group-Avnet 0:478cfd88041f 925 #define CHFLT_40_6 ((uint8_t)0x64) /*!< RX Channel Filter Bandwidth = 40.6 kHz */
group-Avnet 0:478cfd88041f 926 #define CHFLT_36_7 ((uint8_t)0x74) /*!< RX Channel Filter Bandwidth = 36.7 kHz */
group-Avnet 0:478cfd88041f 927 #define CHFLT_33_7 ((uint8_t)0x84) /*!< RX Channel Filter Bandwidth = 33.7 kHz */
group-Avnet 0:478cfd88041f 928 #define CHFLT_28 ((uint8_t)0x05) /*!< RX Channel Filter Bandwidth = 28.0 kHz */
group-Avnet 0:478cfd88041f 929 #define CHFLT_26_5 ((uint8_t)0x15) /*!< RX Channel Filter Bandwidth = 26.5 kHz */
group-Avnet 0:478cfd88041f 930 #define CHFLT_25_1 ((uint8_t)0x25) /*!< RX Channel Filter Bandwidth = 25.1 kHz */
group-Avnet 0:478cfd88041f 931 #define CHFLT_23_7 ((uint8_t)0x35) /*!< RX Channel Filter Bandwidth = 23.7 kHz */
group-Avnet 0:478cfd88041f 932 #define CHFLT_22_6 ((uint8_t)0x45) /*!< RX Channel Filter Bandwidth = 22.6 kHz */
group-Avnet 0:478cfd88041f 933 #define CHFLT_21_3 ((uint8_t)0x55) /*!< RX Channel Filter Bandwidth = 21.3 kHz */
group-Avnet 0:478cfd88041f 934 #define CHFLT_20_3 ((uint8_t)0x65) /*!< RX Channel Filter Bandwidth = 20.3 kHz */
group-Avnet 0:478cfd88041f 935 #define CHFLT_18_4 ((uint8_t)0x75) /*!< RX Channel Filter Bandwidth = 18.4 kHz */
group-Avnet 0:478cfd88041f 936 #define CHFLT_16_9 ((uint8_t)0x85) /*!< RX Channel Filter Bandwidth = 16.9 kHz */
group-Avnet 0:478cfd88041f 937 #define CHFLT_14 ((uint8_t)0x06) /*!< RX Channel Filter Bandwidth = 14.0 kHz */
group-Avnet 0:478cfd88041f 938 #define CHFLT_13_3 ((uint8_t)0x16) /*!< RX Channel Filter Bandwidth = 13.3 kHz */
group-Avnet 0:478cfd88041f 939 #define CHFLT_12_6 ((uint8_t)0x26) /*!< RX Channel Filter Bandwidth = 12.6 kHz */
group-Avnet 0:478cfd88041f 940 #define CHFLT_11_9 ((uint8_t)0x36) /*!< RX Channel Filter Bandwidth = 11.9 kHz */
group-Avnet 0:478cfd88041f 941 #define CHFLT_11_3 ((uint8_t)0x46) /*!< RX Channel Filter Bandwidth = 11.3 kHz */
group-Avnet 0:478cfd88041f 942 #define CHFLT_10_6 ((uint8_t)0x56) /*!< RX Channel Filter Bandwidth = 10.6 kHz */
group-Avnet 0:478cfd88041f 943 #define CHFLT_10_1 ((uint8_t)0x66) /*!< RX Channel Filter Bandwidth = 10.1 kHz */
group-Avnet 0:478cfd88041f 944 #define CHFLT_9_2 ((uint8_t)0x76) /*!< RX Channel Filter Bandwidth = 9.2 kHz */
group-Avnet 0:478cfd88041f 945 #define CHFLT_8_4 ((uint8_t)0x86) /*!< RX Channel Filter Bandwidth = 8.4 kHz */
group-Avnet 0:478cfd88041f 946 #define CHFLT_7 ((uint8_t)0x07) /*!< RX Channel Filter Bandwidth = 7.0 kHz */
group-Avnet 0:478cfd88041f 947 #define CHFLT_6_6 ((uint8_t)0x17) /*!< RX Channel Filter Bandwidth = 6.6 kHz */
group-Avnet 0:478cfd88041f 948 #define CHFLT_6_3 ((uint8_t)0x27) /*!< RX Channel Filter Bandwidth = 6.3 kHz */
group-Avnet 0:478cfd88041f 949 #define CHFLT_5_9 ((uint8_t)0x37) /*!< RX Channel Filter Bandwidth = 5.9 kHz */
group-Avnet 0:478cfd88041f 950 #define CHFLT_5_6 ((uint8_t)0x47) /*!< RX Channel Filter Bandwidth = 5.6 kHz */
group-Avnet 0:478cfd88041f 951 #define CHFLT_5_3 ((uint8_t)0x57) /*!< RX Channel Filter Bandwidth = 5.3 kHz */
group-Avnet 0:478cfd88041f 952 #define CHFLT_5_1 ((uint8_t)0x67) /*!< RX Channel Filter Bandwidth = 5.1 kHz */
group-Avnet 0:478cfd88041f 953 #define CHFLT_4_6 ((uint8_t)0x77) /*!< RX Channel Filter Bandwidth = 4.6 kHz */
group-Avnet 0:478cfd88041f 954 #define CHFLT_4_2 ((uint8_t)0x87) /*!< RX Channel Filter Bandwidth = 4.2 kHz */
group-Avnet 0:478cfd88041f 955 #define CHFLT_3_5 ((uint8_t)0x08) /*!< RX Channel Filter Bandwidth = 3.5 kHz */
group-Avnet 0:478cfd88041f 956 #define CHFLT_3_3 ((uint8_t)0x18) /*!< RX Channel Filter Bandwidth = 3.3 kHz */
group-Avnet 0:478cfd88041f 957 #define CHFLT_3_1 ((uint8_t)0x28) /*!< RX Channel Filter Bandwidth = 3.1 kHz */
group-Avnet 0:478cfd88041f 958 #define CHFLT_3 ((uint8_t)0x38) /*!< RX Channel Filter Bandwidth = 3.0 kHz */
group-Avnet 0:478cfd88041f 959 #define CHFLT_2_8 ((uint8_t)0x48) /*!< RX Channel Filter Bandwidth = 2.8 kHz */
group-Avnet 0:478cfd88041f 960 #define CHFLT_2_7 ((uint8_t)0x58) /*!< RX Channel Filter Bandwidth = 2.7 kHz */
group-Avnet 0:478cfd88041f 961 #define CHFLT_2_5 ((uint8_t)0x68) /*!< RX Channel Filter Bandwidth = 2.5 kHz */
group-Avnet 0:478cfd88041f 962 #define CHFLT_2_3 ((uint8_t)0x78) /*!< RX Channel Filter Bandwidth = 2.3 kHz */
group-Avnet 0:478cfd88041f 963 #define CHFLT_2_1 ((uint8_t)0x88) /*!< RX Channel Filter Bandwidth = 2.1 kHz */
group-Avnet 0:478cfd88041f 964 #define CHFLT_1_8 ((uint8_t)0x09) /*!< RX Channel Filter Bandwidth = 1.8 kHz */
group-Avnet 0:478cfd88041f 965 #define CHFLT_1_7 ((uint8_t)0x19) /*!< RX Channel Filter Bandwidth = 1.7 kHz */
group-Avnet 0:478cfd88041f 966 #define CHFLT_1_6 ((uint8_t)0x29) /*!< RX Channel Filter Bandwidth = 1.6 kHz */
group-Avnet 0:478cfd88041f 967 #define CHFLT_1_5 ((uint8_t)0x39) /*!< RX Channel Filter Bandwidth = 1.5 kHz */
group-Avnet 0:478cfd88041f 968 #define CHFLT_1_4 ((uint8_t)0x49) /*!< RX Channel Filter Bandwidth = 1.4 kHz */
group-Avnet 0:478cfd88041f 969 #define CHFLT_1_3a ((uint8_t)0x59) /*!< RX Channel Filter Bandwidth = 1.3 kHz */
group-Avnet 0:478cfd88041f 970 #define CHFLT_1_3 ((uint8_t)0x69) /*!< RX Channel Filter Bandwidth = 1.3 kHz */
group-Avnet 0:478cfd88041f 971 #define CHFLT_1_2 ((uint8_t)0x79) /*!< RX Channel Filter Bandwidth = 1.2 kHz */
group-Avnet 0:478cfd88041f 972 #define CHFLT_1_1 ((uint8_t)0x89) /*!< RX Channel Filter Bandwidth = 1.1 kHz */
group-Avnet 0:478cfd88041f 973
group-Avnet 0:478cfd88041f 974 /**
group-Avnet 0:478cfd88041f 975 * @}
group-Avnet 0:478cfd88041f 976 */
group-Avnet 0:478cfd88041f 977
group-Avnet 0:478cfd88041f 978 /** @defgroup AFC2_Register
group-Avnet 0:478cfd88041f 979 * @{
group-Avnet 0:478cfd88041f 980 */
group-Avnet 0:478cfd88041f 981
group-Avnet 0:478cfd88041f 982 /**
group-Avnet 0:478cfd88041f 983 * \brief AFC2 register
group-Avnet 0:478cfd88041f 984 * \code
group-Avnet 0:478cfd88041f 985 * Read Write
group-Avnet 0:478cfd88041f 986 * Default value: 0x48
group-Avnet 0:478cfd88041f 987 * 7 AFC Freeze on Sync: Freeze AFC correction upon sync word detection.
group-Avnet 0:478cfd88041f 988 * 1 - AFC Freeze enabled
group-Avnet 0:478cfd88041f 989 * 0 - AFC Freeze disabled
group-Avnet 0:478cfd88041f 990 *
group-Avnet 0:478cfd88041f 991 * 6 AFC Enabled: Enable AFC
group-Avnet 0:478cfd88041f 992 * 1 - AFC enabled
group-Avnet 0:478cfd88041f 993 * 0 - AFC disabled
group-Avnet 0:478cfd88041f 994 *
group-Avnet 0:478cfd88041f 995 * 5 AFC Mode: Select AFC mode
group-Avnet 0:478cfd88041f 996 * 1 - AFC Loop closed on 2nd conversion stage.
group-Avnet 0:478cfd88041f 997 * 0 - AFC Loop closed on slicer
group-Avnet 0:478cfd88041f 998 *
group-Avnet 0:478cfd88041f 999 * 4:0 AFC PD leakage[4:0]: Peak detector leakage. This parameter sets the decay speed of the min/max frequency peak detector (AFC2 register),
group-Avnet 0:478cfd88041f 1000 * the range allowed is 0..31 (0 - no leakage, 31 - high leakage). The recommended value for this parameter is 4.
group-Avnet 0:478cfd88041f 1001 *
group-Avnet 0:478cfd88041f 1002 * \endcode
group-Avnet 0:478cfd88041f 1003 */
group-Avnet 0:478cfd88041f 1004 #define AFC2_BASE ((uint8_t)0x1E) /*!< Automatic frequency compensation algorithm parameters (FSK/GFSK/MSK)*/
group-Avnet 0:478cfd88041f 1005
group-Avnet 0:478cfd88041f 1006 #define AFC2_AFC_FREEZE_ON_SYNC_MASK ((uint8_t)0x80) /*!< The frequency correction value is frozen when SYNC word is detected */
group-Avnet 0:478cfd88041f 1007 #define AFC2_AFC_MASK ((uint8_t)0x40) /*!< Mask of Automatic Frequency Correction */
group-Avnet 0:478cfd88041f 1008 #define AFC2_AFC_MODE_MASK ((uint8_t)0x20) /*!< Automatic Frequency Correction can be in Main MODE or Auxiliary MODE*/
group-Avnet 0:478cfd88041f 1009 #define AFC2_AFC_MODE_SLICER ((uint8_t)0x00) /*!< Automatic Frequency Correction Main MODE */
group-Avnet 0:478cfd88041f 1010 #define AFC2_AFC_MODE_MIXER ((uint8_t)0x20) /*!< Automatic Frequency Correction Auxiliary MODE */
group-Avnet 0:478cfd88041f 1011
group-Avnet 0:478cfd88041f 1012 /**
group-Avnet 0:478cfd88041f 1013 * @}
group-Avnet 0:478cfd88041f 1014 */
group-Avnet 0:478cfd88041f 1015
group-Avnet 0:478cfd88041f 1016 /** @defgroup AFC1_Register
group-Avnet 0:478cfd88041f 1017 * @{
group-Avnet 0:478cfd88041f 1018 */
group-Avnet 0:478cfd88041f 1019
group-Avnet 0:478cfd88041f 1020 /**
group-Avnet 0:478cfd88041f 1021 * \brief AFC1 register
group-Avnet 0:478cfd88041f 1022 * \code
group-Avnet 0:478cfd88041f 1023 * Read Write
group-Avnet 0:478cfd88041f 1024 * Default value: 0x18
group-Avnet 0:478cfd88041f 1025 * 7:0 AFC_FAST_PERIOD: Length of the AFC fast period. this parameter sets the length of the fast period in number of samples (AFC1 register), the range allowed
group-Avnet 0:478cfd88041f 1026 * is 0..255. The recommended setting for this parameter is such that the fast period equals the preamble length. Since the
group-Avnet 0:478cfd88041f 1027 * algorithm operates typically on 2 samples per symbol, the programmed value should be twice the number of preamble
group-Avnet 0:478cfd88041f 1028 * symbols.
group-Avnet 0:478cfd88041f 1029 *
group-Avnet 0:478cfd88041f 1030 * \endcode
group-Avnet 0:478cfd88041f 1031 */
group-Avnet 0:478cfd88041f 1032 #define AFC1_BASE ((uint8_t)0x1F) /*!< Length of the AFC fast period */
group-Avnet 0:478cfd88041f 1033
group-Avnet 0:478cfd88041f 1034 /**
group-Avnet 0:478cfd88041f 1035 * @}
group-Avnet 0:478cfd88041f 1036 */
group-Avnet 0:478cfd88041f 1037
group-Avnet 0:478cfd88041f 1038 /** @defgroup AFC0_Register
group-Avnet 0:478cfd88041f 1039 * @{
group-Avnet 0:478cfd88041f 1040 */
group-Avnet 0:478cfd88041f 1041
group-Avnet 0:478cfd88041f 1042 /**
group-Avnet 0:478cfd88041f 1043 * \brief AFC0 register
group-Avnet 0:478cfd88041f 1044 * \code
group-Avnet 0:478cfd88041f 1045 * Read Write
group-Avnet 0:478cfd88041f 1046 * Default value: 0x25
group-Avnet 0:478cfd88041f 1047 * 7:4 AFC_FAST_GAIN_LOG2[3:0]: AFC loop gain in fast mode (2's log)
group-Avnet 0:478cfd88041f 1048 *
group-Avnet 0:478cfd88041f 1049 * 3:0 AFC_SLOW_GAIN_LOG2[3:0]: AFC loop gain in slow mode (2's log)
group-Avnet 0:478cfd88041f 1050 *
group-Avnet 0:478cfd88041f 1051 * \endcode
group-Avnet 0:478cfd88041f 1052 */
group-Avnet 0:478cfd88041f 1053 #define AFC0_BASE ((uint8_t)0x20) /*!< AFC loop gain in fast and slow modes (2's log) */
group-Avnet 0:478cfd88041f 1054
group-Avnet 0:478cfd88041f 1055 /**
group-Avnet 0:478cfd88041f 1056 * @}
group-Avnet 0:478cfd88041f 1057 */
group-Avnet 0:478cfd88041f 1058
group-Avnet 0:478cfd88041f 1059 /** @defgroup CLOCKREC_Register
group-Avnet 0:478cfd88041f 1060 * @{
group-Avnet 0:478cfd88041f 1061 */
group-Avnet 0:478cfd88041f 1062
group-Avnet 0:478cfd88041f 1063 /**
group-Avnet 0:478cfd88041f 1064 * \brief CLOCKREC register
group-Avnet 0:478cfd88041f 1065 * \code
group-Avnet 0:478cfd88041f 1066 * Read Write
group-Avnet 0:478cfd88041f 1067 * Default value: 0x58
group-Avnet 0:478cfd88041f 1068 *
group-Avnet 0:478cfd88041f 1069 * 7:5 CLK_REC_P_GAIN [2:0]: Clock recovery loop gain (log2)
group-Avnet 0:478cfd88041f 1070 *
group-Avnet 0:478cfd88041f 1071 * 4 PSTFLT_LEN: Set Postfilter length
group-Avnet 0:478cfd88041f 1072 * 1 - 16 symbols
group-Avnet 0:478cfd88041f 1073 * 0 - 8 symbols
group-Avnet 0:478cfd88041f 1074 *
group-Avnet 0:478cfd88041f 1075 * 3:0 CLK_REC_I_GAIN[3:0]: Integral gain for the clock recovery loop
group-Avnet 0:478cfd88041f 1076 * \endcode
group-Avnet 0:478cfd88041f 1077 */
group-Avnet 0:478cfd88041f 1078
group-Avnet 0:478cfd88041f 1079 #define CLOCKREC_BASE ((uint8_t)0x23) /*!< Gain of clock recovery loop - Postfilter length 0-8 symbols, 1-16 symbols */
group-Avnet 0:478cfd88041f 1080
group-Avnet 0:478cfd88041f 1081 /**
group-Avnet 0:478cfd88041f 1082 * @}
group-Avnet 0:478cfd88041f 1083 */
group-Avnet 0:478cfd88041f 1084
group-Avnet 0:478cfd88041f 1085 /** @defgroup AGCCTRL2_Register
group-Avnet 0:478cfd88041f 1086 * @{
group-Avnet 0:478cfd88041f 1087 */
group-Avnet 0:478cfd88041f 1088
group-Avnet 0:478cfd88041f 1089 /**
group-Avnet 0:478cfd88041f 1090 * \brief AGCCTRL2 register
group-Avnet 0:478cfd88041f 1091 * \code
group-Avnet 0:478cfd88041f 1092 * Read Write
group-Avnet 0:478cfd88041f 1093 * Default value: 0x22
group-Avnet 0:478cfd88041f 1094 *
group-Avnet 0:478cfd88041f 1095 * 7 Reserved
group-Avnet 0:478cfd88041f 1096 *
group-Avnet 0:478cfd88041f 1097 * 6 FREEZE_ON_STEADY: Enable freezing on steady state
group-Avnet 0:478cfd88041f 1098 * 1 - Enable
group-Avnet 0:478cfd88041f 1099 * 0 - Disable
group-Avnet 0:478cfd88041f 1100 *
group-Avnet 0:478cfd88041f 1101 * 5 FREEZE_ON_SYNC: Enable freezing on sync detection
group-Avnet 0:478cfd88041f 1102 * 1 - Enable
group-Avnet 0:478cfd88041f 1103 * 0 - Disable
group-Avnet 0:478cfd88041f 1104 *
group-Avnet 0:478cfd88041f 1105 * 4 START_MAX_ATTENUATION: Start with max attenuation
group-Avnet 0:478cfd88041f 1106 * 1 - Enable
group-Avnet 0:478cfd88041f 1107 * 0 - Disable
group-Avnet 0:478cfd88041f 1108 *
group-Avnet 0:478cfd88041f 1109 * 3:0 MEAS_TIME[3:0]: Measure time during which the signal peak is detected (according to the formula 12/fxo*2^MEAS_TIME)
group-Avnet 0:478cfd88041f 1110 * \endcode
group-Avnet 0:478cfd88041f 1111 */
group-Avnet 0:478cfd88041f 1112 #define AGCCTRL2_BASE ((uint8_t)0x24) /*!< AGC freeze strategy, AGC attenuation strategy, AGC measure time */
group-Avnet 0:478cfd88041f 1113
group-Avnet 0:478cfd88041f 1114 #define AGCCTRL2_FREEZE_ON_STEADY_MASK ((uint8_t)0x40) /*!< The attenuation settings will be frozen as soon as signal level
group-Avnet 0:478cfd88041f 1115 is betweeen min and max treshold (see AGCCTRL1) */
group-Avnet 0:478cfd88041f 1116 #define AGCCTRL2_FREEZE_ON_SYNC_MASK ((uint8_t)0x20) /*!< The attenuation settings will be frozen as soon sync word is detected */
group-Avnet 0:478cfd88041f 1117 #define AGCCTRL2_START_MAX_ATTENUATION_MASK ((uint8_t)0x10) /*!< The AGC algorithm can start with MAX attenuation or MIN attenuation */
group-Avnet 0:478cfd88041f 1118
group-Avnet 0:478cfd88041f 1119 /**
group-Avnet 0:478cfd88041f 1120 * @}
group-Avnet 0:478cfd88041f 1121 */
group-Avnet 0:478cfd88041f 1122
group-Avnet 0:478cfd88041f 1123 /** @defgroup AGCCTRL1_Register
group-Avnet 0:478cfd88041f 1124 * @{
group-Avnet 0:478cfd88041f 1125 */
group-Avnet 0:478cfd88041f 1126
group-Avnet 0:478cfd88041f 1127 /**
group-Avnet 0:478cfd88041f 1128 * \brief AGCCTRL1 register
group-Avnet 0:478cfd88041f 1129 * \code
group-Avnet 0:478cfd88041f 1130 * Read Write
group-Avnet 0:478cfd88041f 1131 * Default value: 0x65
group-Avnet 0:478cfd88041f 1132 *
group-Avnet 0:478cfd88041f 1133 * 7:4 THRESHOLD_HIGH[3:0]: High threshold for the AGC
group-Avnet 0:478cfd88041f 1134 *
group-Avnet 0:478cfd88041f 1135 * 3:0 THRESHOLD_LOW[3:0]: Low threshold for the AGC
group-Avnet 0:478cfd88041f 1136 * \endcode
group-Avnet 0:478cfd88041f 1137 */
group-Avnet 0:478cfd88041f 1138 #define AGCCTRL1_BASE ((uint8_t)0x25) /*!< Sets low and high threshold for AGC */
group-Avnet 0:478cfd88041f 1139
group-Avnet 0:478cfd88041f 1140 /**
group-Avnet 0:478cfd88041f 1141 * @}
group-Avnet 0:478cfd88041f 1142 */
group-Avnet 0:478cfd88041f 1143
group-Avnet 0:478cfd88041f 1144 /** @defgroup AGCCTRL0_Register
group-Avnet 0:478cfd88041f 1145 * @{
group-Avnet 0:478cfd88041f 1146 */
group-Avnet 0:478cfd88041f 1147
group-Avnet 0:478cfd88041f 1148 /**
group-Avnet 0:478cfd88041f 1149 * \brief AGCCTRL0 register
group-Avnet 0:478cfd88041f 1150 * \code
group-Avnet 0:478cfd88041f 1151 * Read Write
group-Avnet 0:478cfd88041f 1152 * Default value: 0x8A
group-Avnet 0:478cfd88041f 1153 *
group-Avnet 0:478cfd88041f 1154 * 7 AGC S_ENABLE: Enable AGC
group-Avnet 0:478cfd88041f 1155 * 1 - Enable
group-Avnet 0:478cfd88041f 1156 * 0 - Disable
group-Avnet 0:478cfd88041f 1157 *
group-Avnet 0:478cfd88041f 1158 * 6 AGC_MODE: Set linear-Binary AGC mode
group-Avnet 0:478cfd88041f 1159 * 1 - Enable
group-Avnet 0:478cfd88041f 1160 * 0 - Disable
group-Avnet 0:478cfd88041f 1161 *
group-Avnet 0:478cfd88041f 1162 * 5:0 HOLD_TIME[5:0]: Hold time after gain adjustment according to formula 12/fxo*HOLD_TIME
group-Avnet 0:478cfd88041f 1163 * \endcode
group-Avnet 0:478cfd88041f 1164 */
group-Avnet 0:478cfd88041f 1165 #define AGCCTRL0_BASE ((uint8_t)0x26) /*!< Enables AGC, set AGC algo between linear/binary mode, set hold time
group-Avnet 0:478cfd88041f 1166 to account signal propagation through RX chain */
group-Avnet 0:478cfd88041f 1167 #define AGCCTRL0_AGC_MASK ((uint8_t)0x80) /*!< AGC on/off */
group-Avnet 0:478cfd88041f 1168 #define AGCCTRL0_AGC_MODE_MASK ((uint8_t)0x40) /*!< AGC search correct attenuation in binary mode or sequential mode */
group-Avnet 0:478cfd88041f 1169 #define AGCCTRL0_AGC_MODE_LINEAR ((uint8_t)0x00) /*!< AGC search correct attenuation in sequential mode (recommended) */
group-Avnet 0:478cfd88041f 1170 #define AGCCTRL0_AGC_MODE_BINARY ((uint8_t)0x40) /*!< AGC search correct attenuation in binary mode */
group-Avnet 0:478cfd88041f 1171
group-Avnet 0:478cfd88041f 1172 /**
group-Avnet 0:478cfd88041f 1173 * @}
group-Avnet 0:478cfd88041f 1174 */
group-Avnet 0:478cfd88041f 1175
group-Avnet 0:478cfd88041f 1176 /** @defgroup CHNUM_Register
group-Avnet 0:478cfd88041f 1177 * @{
group-Avnet 0:478cfd88041f 1178 */
group-Avnet 0:478cfd88041f 1179
group-Avnet 0:478cfd88041f 1180 /**
group-Avnet 0:478cfd88041f 1181 * \brief CHNUM registers
group-Avnet 0:478cfd88041f 1182 * \code
group-Avnet 0:478cfd88041f 1183 * Default value: 0x00
group-Avnet 0:478cfd88041f 1184 * Read Write
group-Avnet 0:478cfd88041f 1185 * 7:0 CH_NUM[7:0]: Channel number. This value is multiplied by the channel spacing and added to the
group-Avnet 0:478cfd88041f 1186 * synthesizer base frequency to generate the actual RF carrier frequency.
group-Avnet 0:478cfd88041f 1187 * \endcode
group-Avnet 0:478cfd88041f 1188 */
group-Avnet 0:478cfd88041f 1189 #define CHNUM_BASE ((uint8_t)0x6C) /*!< Channel number. This value is multiplied by the channel
group-Avnet 0:478cfd88041f 1190 spacing and added to the synthesizer base frequency to generate the actual RF carrier frequency */
group-Avnet 0:478cfd88041f 1191 /**
group-Avnet 0:478cfd88041f 1192 * @}
group-Avnet 0:478cfd88041f 1193 */
group-Avnet 0:478cfd88041f 1194
group-Avnet 0:478cfd88041f 1195 /** @defgroup AFC_CORR_Register
group-Avnet 0:478cfd88041f 1196 * @{
group-Avnet 0:478cfd88041f 1197 */
group-Avnet 0:478cfd88041f 1198
group-Avnet 0:478cfd88041f 1199 /**
group-Avnet 0:478cfd88041f 1200 * \brief AFC_CORR registers
group-Avnet 0:478cfd88041f 1201 * \code
group-Avnet 0:478cfd88041f 1202 * Default value: 0x00
group-Avnet 0:478cfd88041f 1203 * Read
group-Avnet 0:478cfd88041f 1204 *
group-Avnet 0:478cfd88041f 1205 * 7:0 AFC_CORR[7:0]: AFC word of the received packet
group-Avnet 0:478cfd88041f 1206 * \endcode
group-Avnet 0:478cfd88041f 1207 */
group-Avnet 0:478cfd88041f 1208 #define AFC_CORR_BASE ((uint8_t)(0xC4)) /*!< AFC word of the received packet */
group-Avnet 0:478cfd88041f 1209
group-Avnet 0:478cfd88041f 1210 /**
group-Avnet 0:478cfd88041f 1211 * @}
group-Avnet 0:478cfd88041f 1212 */
group-Avnet 0:478cfd88041f 1213
group-Avnet 0:478cfd88041f 1214 /**
group-Avnet 0:478cfd88041f 1215 * @}
group-Avnet 0:478cfd88041f 1216 */
group-Avnet 0:478cfd88041f 1217
group-Avnet 0:478cfd88041f 1218
group-Avnet 0:478cfd88041f 1219 /** @defgroup Packet_Configuration_Registers
group-Avnet 0:478cfd88041f 1220 * @{
group-Avnet 0:478cfd88041f 1221 */
group-Avnet 0:478cfd88041f 1222
group-Avnet 0:478cfd88041f 1223 /** @defgroup PCKTCTRL4_Register
group-Avnet 0:478cfd88041f 1224 * @{
group-Avnet 0:478cfd88041f 1225 */
group-Avnet 0:478cfd88041f 1226
group-Avnet 0:478cfd88041f 1227 /**
group-Avnet 0:478cfd88041f 1228 * \brief PCKTCTRL4 register
group-Avnet 0:478cfd88041f 1229 * \code
group-Avnet 0:478cfd88041f 1230 * Read Write
group-Avnet 0:478cfd88041f 1231 * Default value: 0x00
group-Avnet 0:478cfd88041f 1232 *
group-Avnet 0:478cfd88041f 1233 * 7:5 NOT_USED.
group-Avnet 0:478cfd88041f 1234 *
group-Avnet 0:478cfd88041f 1235 * 4:3 ADDRESS_LEN[1:0]: length of address field in bytes
group-Avnet 0:478cfd88041f 1236 *
group-Avnet 0:478cfd88041f 1237 * 2:0 control_len[2:0]: length of control field in bytes
group-Avnet 0:478cfd88041f 1238 * \endcode
group-Avnet 0:478cfd88041f 1239 */
group-Avnet 0:478cfd88041f 1240 #define PCKTCTRL4_BASE ((uint8_t)0x30) /*!< lenghts of address and control field */
group-Avnet 0:478cfd88041f 1241
group-Avnet 0:478cfd88041f 1242 #define PCKTCTRL4_ADDRESS_LEN_MASK ((uint8_t)0x18)
group-Avnet 0:478cfd88041f 1243 #define PCKTCTRL4_CONTROL_LEN_MASK ((uint8_t)0x07)
group-Avnet 0:478cfd88041f 1244
group-Avnet 0:478cfd88041f 1245 /**
group-Avnet 0:478cfd88041f 1246 * @}
group-Avnet 0:478cfd88041f 1247 */
group-Avnet 0:478cfd88041f 1248
group-Avnet 0:478cfd88041f 1249 /** @defgroup PCKTCTRL3_Register
group-Avnet 0:478cfd88041f 1250 * @{
group-Avnet 0:478cfd88041f 1251 */
group-Avnet 0:478cfd88041f 1252
group-Avnet 0:478cfd88041f 1253 /**
group-Avnet 0:478cfd88041f 1254 * \brief PCKTCTRL3 register
group-Avnet 0:478cfd88041f 1255 * \code
group-Avnet 0:478cfd88041f 1256 * Read Write
group-Avnet 0:478cfd88041f 1257 * Default value: 0x07
group-Avnet 0:478cfd88041f 1258 *
group-Avnet 0:478cfd88041f 1259 * 7:6 PCKT_FRMT[1:0]: format of packet
group-Avnet 0:478cfd88041f 1260 *
group-Avnet 0:478cfd88041f 1261 * PCKT_FRMT1 | PCKT_FRMT0 | Format
group-Avnet 0:478cfd88041f 1262 * ----------------------------------------------------------------------
group-Avnet 0:478cfd88041f 1263 * 0 | 0 | BASIC
group-Avnet 0:478cfd88041f 1264 * 1 | 0 | MBUS
group-Avnet 0:478cfd88041f 1265 * 1 | 1 | STACK
group-Avnet 0:478cfd88041f 1266 *
group-Avnet 0:478cfd88041f 1267 * 5:4 RX_MODE[1:0]: length of address 0x30 field in bytes
group-Avnet 0:478cfd88041f 1268 *
group-Avnet 0:478cfd88041f 1269 * RX_MODE1 | RX_MODE0 | Rx Mode
group-Avnet 0:478cfd88041f 1270 * --------------------------------------------------------------------
group-Avnet 0:478cfd88041f 1271 * 0 | 0 | normal
group-Avnet 0:478cfd88041f 1272 * 0 | 1 | direct through FIFO
group-Avnet 0:478cfd88041f 1273 * 1 | 0 | direct through GPIO
group-Avnet 0:478cfd88041f 1274 *
group-Avnet 0:478cfd88041f 1275 * 3:0 LEN_WID[3:0]: length of length field in bits
group-Avnet 0:478cfd88041f 1276 * \endcode
group-Avnet 0:478cfd88041f 1277 */
group-Avnet 0:478cfd88041f 1278 #define PCKTCTRL3_BASE ((uint8_t)0x31) /*!< packet format, RX mode, lenght of length field */
group-Avnet 0:478cfd88041f 1279
group-Avnet 0:478cfd88041f 1280 #define PCKTCTRL3_PCKT_FRMT_BASIC ((uint8_t)0x00) /*!< Basic Packet Format */
group-Avnet 0:478cfd88041f 1281 #define PCKTCTRL3_PCKT_FRMT_MBUS ((uint8_t)0x80) /*!< Wireless M-BUS Packet Format */
group-Avnet 0:478cfd88041f 1282 #define PCKTCTRL3_PCKT_FRMT_STACK ((uint8_t)0xC0) /*!< STack Packet Format */
group-Avnet 0:478cfd88041f 1283
group-Avnet 0:478cfd88041f 1284 #define PCKTCTRL3_RX_MODE_NORMAL ((uint8_t)0x00) /*!< Normal RX Mode */
group-Avnet 0:478cfd88041f 1285 #define PCKTCTRL3_RX_MODE_DIRECT_FIFO ((uint8_t)0x10) /*!< RX Direct Mode; data available through FIFO */
group-Avnet 0:478cfd88041f 1286 #define PCKTCTRL3_RX_MODE_DIRECT_GPIO ((uint8_t)0x20) /*!< RX Direct Mode; data available through selected GPIO */
group-Avnet 0:478cfd88041f 1287
group-Avnet 0:478cfd88041f 1288 #define PCKTCTRL3_PKT_FRMT_MASK ((uint8_t)0xC0)
group-Avnet 0:478cfd88041f 1289 #define PCKTCTRL3_RX_MODE_MASK ((uint8_t)0x30)
group-Avnet 0:478cfd88041f 1290 #define PCKTCTRL3_LEN_WID_MASK ((uint8_t)0x0F)
group-Avnet 0:478cfd88041f 1291
group-Avnet 0:478cfd88041f 1292 /**
group-Avnet 0:478cfd88041f 1293 * @}
group-Avnet 0:478cfd88041f 1294 */
group-Avnet 0:478cfd88041f 1295
group-Avnet 0:478cfd88041f 1296 /** @defgroup PCKTCTRL2_Register
group-Avnet 0:478cfd88041f 1297 * @{
group-Avnet 0:478cfd88041f 1298 */
group-Avnet 0:478cfd88041f 1299
group-Avnet 0:478cfd88041f 1300 /**
group-Avnet 0:478cfd88041f 1301 * \brief PCKTCTRL2 register
group-Avnet 0:478cfd88041f 1302 * \code
group-Avnet 0:478cfd88041f 1303 * Read Write
group-Avnet 0:478cfd88041f 1304 * Default value: 0x1E
group-Avnet 0:478cfd88041f 1305 *
group-Avnet 0:478cfd88041f 1306 * 7:3 PREAMBLE_LENGTH[4:0]: length of preamble field in bytes (0..31)
group-Avnet 0:478cfd88041f 1307 *
group-Avnet 0:478cfd88041f 1308 *
group-Avnet 0:478cfd88041f 1309 * 2:1 SYNC_LENGTH[1:0]: length of sync field in bytes
group-Avnet 0:478cfd88041f 1310 *
group-Avnet 0:478cfd88041f 1311 *
group-Avnet 0:478cfd88041f 1312 * 0 FIX_VAR_LEN: fixed/variable packet length
group-Avnet 0:478cfd88041f 1313 * 1 - Variable
group-Avnet 0:478cfd88041f 1314 * 0 - Fixed
group-Avnet 0:478cfd88041f 1315 * \endcode
group-Avnet 0:478cfd88041f 1316 */
group-Avnet 0:478cfd88041f 1317 #define PCKTCTRL2_BASE ((uint8_t)0x32) /*!< length of preamble and sync fields (in bytes), fix or variable packet length */
group-Avnet 0:478cfd88041f 1318
group-Avnet 0:478cfd88041f 1319 #define PCKTCTRL2_FIX_VAR_LEN_MASK ((uint8_t)0x01) /*!< Enable/disable the length mode */
group-Avnet 0:478cfd88041f 1320 #define PCKTCTRL2_PREAMBLE_LENGTH_MASK ((uint8_t)0xF8)
group-Avnet 0:478cfd88041f 1321 #define PCKTCTRL2_SYNC_LENGTH_MASK ((uint8_t)0x06)
group-Avnet 0:478cfd88041f 1322
group-Avnet 0:478cfd88041f 1323 /**
group-Avnet 0:478cfd88041f 1324 * @}
group-Avnet 0:478cfd88041f 1325 */
group-Avnet 0:478cfd88041f 1326
group-Avnet 0:478cfd88041f 1327 /** @defgroup PCKTCTRL1_Register
group-Avnet 0:478cfd88041f 1328 * @{
group-Avnet 0:478cfd88041f 1329 */
group-Avnet 0:478cfd88041f 1330
group-Avnet 0:478cfd88041f 1331 /**
group-Avnet 0:478cfd88041f 1332 * \brief PCKTCTRL1 register
group-Avnet 0:478cfd88041f 1333 * \code
group-Avnet 0:478cfd88041f 1334 * Read Write
group-Avnet 0:478cfd88041f 1335 * Default value: 0x20
group-Avnet 0:478cfd88041f 1336 *
group-Avnet 0:478cfd88041f 1337 * 7:5 CRC_MODE[2:0]: CRC type (0, 8, 16, 24 bits)
group-Avnet 0:478cfd88041f 1338 *
group-Avnet 0:478cfd88041f 1339 * CRC_MODE2 | CRC_MODE1 | CRC_MODE0 | CRC Mode (n. bits - poly)
group-Avnet 0:478cfd88041f 1340 * -------------------------------------------------------------------------------------------------
group-Avnet 0:478cfd88041f 1341 * 0 | 0 | 1 | 8 - 0x07
group-Avnet 0:478cfd88041f 1342 * 0 | 1 | 0 | 16 - 0x8005
group-Avnet 0:478cfd88041f 1343 * 0 | 1 | 1 | 16 - 0x1021
group-Avnet 0:478cfd88041f 1344 * 1 | 0 | 0 | 24 - 0x864CBF
group-Avnet 0:478cfd88041f 1345 *
group-Avnet 0:478cfd88041f 1346 * 4 WHIT_EN[0]: Enable Whitening
group-Avnet 0:478cfd88041f 1347 * 1 - Enable
group-Avnet 0:478cfd88041f 1348 * 0 - Disable
group-Avnet 0:478cfd88041f 1349 *
group-Avnet 0:478cfd88041f 1350 * 3:2 TX_SOURCE[1:0]: length of sync field in bytes
group-Avnet 0:478cfd88041f 1351 *
group-Avnet 0:478cfd88041f 1352 * TX_SOURCE1 | TX_SOURCE0 | Tx Mode
group-Avnet 0:478cfd88041f 1353 * --------------------------------------------------------------------
group-Avnet 0:478cfd88041f 1354 * 0 | 0 | normal
group-Avnet 0:478cfd88041f 1355 * 0 | 1 | direct through FIFO
group-Avnet 0:478cfd88041f 1356 * 1 | 0 | direct through GPIO
group-Avnet 0:478cfd88041f 1357 * 1 | 1 | pn9
group-Avnet 0:478cfd88041f 1358 *
group-Avnet 0:478cfd88041f 1359 * 1 NOT_USED
group-Avnet 0:478cfd88041f 1360 *
group-Avnet 0:478cfd88041f 1361 * 0 FEC_EN: enable FEC
group-Avnet 0:478cfd88041f 1362 * 1 - FEC in TX , Viterbi decoding in RX
group-Avnet 0:478cfd88041f 1363 * 0 - Disabled
group-Avnet 0:478cfd88041f 1364 * \endcode
group-Avnet 0:478cfd88041f 1365 */
group-Avnet 0:478cfd88041f 1366 #define PCKTCTRL1_BASE ((uint8_t)0x33) /*!< CRC type, whitening enable, TX mode */
group-Avnet 0:478cfd88041f 1367
group-Avnet 0:478cfd88041f 1368 #define PCKTCTRL1_FEC_MASK ((uint8_t)0x01) /*!< Enable/disable the Forward Error Correction */
group-Avnet 0:478cfd88041f 1369 #define PCKTCTRL1_TX_SOURCE_MASK ((uint8_t)0x0C) /*!< TX source mode */
group-Avnet 0:478cfd88041f 1370 #define PCKTCTRL1_CRC_MODE_MASK ((uint8_t)0xE0) /*!< CRC type */
group-Avnet 0:478cfd88041f 1371 #define PCKTCTRL1_WHIT_MASK ((uint8_t)0x10) /*!< Enable/disable the Whitening */
group-Avnet 0:478cfd88041f 1372
group-Avnet 0:478cfd88041f 1373 /**
group-Avnet 0:478cfd88041f 1374 * @}
group-Avnet 0:478cfd88041f 1375 */
group-Avnet 0:478cfd88041f 1376
group-Avnet 0:478cfd88041f 1377
group-Avnet 0:478cfd88041f 1378
group-Avnet 0:478cfd88041f 1379 /** @defgroup PCKTLEN1_Register
group-Avnet 0:478cfd88041f 1380 * @{
group-Avnet 0:478cfd88041f 1381 */
group-Avnet 0:478cfd88041f 1382
group-Avnet 0:478cfd88041f 1383 /**
group-Avnet 0:478cfd88041f 1384 * \brief PCKTLEN1 register
group-Avnet 0:478cfd88041f 1385 * \code
group-Avnet 0:478cfd88041f 1386 * Read Write
group-Avnet 0:478cfd88041f 1387 * Default value: 0x00
group-Avnet 0:478cfd88041f 1388 *
group-Avnet 0:478cfd88041f 1389 * 7:0 pktlen1[7:0]: lenght of packet in bytes (upper field) LENGHT/256
group-Avnet 0:478cfd88041f 1390 * \endcode
group-Avnet 0:478cfd88041f 1391 */
group-Avnet 0:478cfd88041f 1392 #define PCKTLEN1_BASE ((uint8_t)0x34) /*!< lenght of packet in bytes (upper field) */
group-Avnet 0:478cfd88041f 1393
group-Avnet 0:478cfd88041f 1394 /**
group-Avnet 0:478cfd88041f 1395 * @}
group-Avnet 0:478cfd88041f 1396 */
group-Avnet 0:478cfd88041f 1397
group-Avnet 0:478cfd88041f 1398 /** @defgroup PCKTLEN0_Register
group-Avnet 0:478cfd88041f 1399 * @{
group-Avnet 0:478cfd88041f 1400 */
group-Avnet 0:478cfd88041f 1401
group-Avnet 0:478cfd88041f 1402 /**
group-Avnet 0:478cfd88041f 1403 * \brief PCKTLEN0 register
group-Avnet 0:478cfd88041f 1404 * \code
group-Avnet 0:478cfd88041f 1405 * Read Write
group-Avnet 0:478cfd88041f 1406 * Default value: 0x14
group-Avnet 0:478cfd88041f 1407 *
group-Avnet 0:478cfd88041f 1408 * 7:0 pktlen0[7:0]: lenght of packet in bytes (lower field) LENGHT%256
group-Avnet 0:478cfd88041f 1409 * \endcode
group-Avnet 0:478cfd88041f 1410 */
group-Avnet 0:478cfd88041f 1411 #define PCKTLEN0_BASE ((uint8_t)0x35) /*!< lenght of packet in bytes (lower field) [PCKTLEN=PCKTLEN1x256+PCKTLEN0]*/
group-Avnet 0:478cfd88041f 1412
group-Avnet 0:478cfd88041f 1413 /**
group-Avnet 0:478cfd88041f 1414 * @}
group-Avnet 0:478cfd88041f 1415 */
group-Avnet 0:478cfd88041f 1416
group-Avnet 0:478cfd88041f 1417 /** @defgroup SYNCx_Registers
group-Avnet 0:478cfd88041f 1418 * @{
group-Avnet 0:478cfd88041f 1419 */
group-Avnet 0:478cfd88041f 1420 /**
group-Avnet 0:478cfd88041f 1421 * \brief SYNCx[4:1] Registers
group-Avnet 0:478cfd88041f 1422 * \code
group-Avnet 0:478cfd88041f 1423 * Read Write
group-Avnet 0:478cfd88041f 1424 * Default value: 0x88
group-Avnet 0:478cfd88041f 1425 *
group-Avnet 0:478cfd88041f 1426 * 7:0 SYNCx[7:0]: xth sync word
group-Avnet 0:478cfd88041f 1427 * \endcode
group-Avnet 0:478cfd88041f 1428 */
group-Avnet 0:478cfd88041f 1429 #define SYNC4_BASE ((uint8_t)0x36) /*!< Sync word 4 */
group-Avnet 0:478cfd88041f 1430 #define SYNC3_BASE ((uint8_t)0x37) /*!< Sync word 3 */
group-Avnet 0:478cfd88041f 1431 #define SYNC2_BASE ((uint8_t)0x38) /*!< Sync word 2 */
group-Avnet 0:478cfd88041f 1432 #define SYNC1_BASE ((uint8_t)0x39) /*!< Sync word 1 */
group-Avnet 0:478cfd88041f 1433
group-Avnet 0:478cfd88041f 1434 /**
group-Avnet 0:478cfd88041f 1435 * @}
group-Avnet 0:478cfd88041f 1436 */
group-Avnet 0:478cfd88041f 1437
group-Avnet 0:478cfd88041f 1438
group-Avnet 0:478cfd88041f 1439 /** @defgroup MBUS_PRMBL_Register
group-Avnet 0:478cfd88041f 1440 * @{
group-Avnet 0:478cfd88041f 1441 */
group-Avnet 0:478cfd88041f 1442
group-Avnet 0:478cfd88041f 1443 /**
group-Avnet 0:478cfd88041f 1444 * \brief MBUS_PRMBL register
group-Avnet 0:478cfd88041f 1445 * \code
group-Avnet 0:478cfd88041f 1446 * Read Write
group-Avnet 0:478cfd88041f 1447 * Default value: 0x20
group-Avnet 0:478cfd88041f 1448 *
group-Avnet 0:478cfd88041f 1449 * 7:0 MBUS_PRMBL[7:0]: MBUS preamble control
group-Avnet 0:478cfd88041f 1450 * \endcode
group-Avnet 0:478cfd88041f 1451 */
group-Avnet 0:478cfd88041f 1452 #define MBUS_PRMBL_BASE ((uint8_t)0x3B) /*!< MBUS preamble lenght (in 01 bit pairs) */
group-Avnet 0:478cfd88041f 1453
group-Avnet 0:478cfd88041f 1454 /**
group-Avnet 0:478cfd88041f 1455 * @}
group-Avnet 0:478cfd88041f 1456 */
group-Avnet 0:478cfd88041f 1457
group-Avnet 0:478cfd88041f 1458
group-Avnet 0:478cfd88041f 1459 /** @defgroup MBUS_PSTMBL_Register
group-Avnet 0:478cfd88041f 1460 * @{
group-Avnet 0:478cfd88041f 1461 */
group-Avnet 0:478cfd88041f 1462
group-Avnet 0:478cfd88041f 1463 /**
group-Avnet 0:478cfd88041f 1464 * \brief MBUS_PSTMBL register
group-Avnet 0:478cfd88041f 1465 * \code
group-Avnet 0:478cfd88041f 1466 * Read Write
group-Avnet 0:478cfd88041f 1467 * Default value: 0x20
group-Avnet 0:478cfd88041f 1468 *
group-Avnet 0:478cfd88041f 1469 * 7:0 MBUS_PSTMBL[7:0]: MBUS postamble control
group-Avnet 0:478cfd88041f 1470 * \endcode
group-Avnet 0:478cfd88041f 1471 */
group-Avnet 0:478cfd88041f 1472 #define MBUS_PSTMBL_BASE ((uint8_t)0x3C) /*!< MBUS postamble length (in 01 bit pairs) */
group-Avnet 0:478cfd88041f 1473
group-Avnet 0:478cfd88041f 1474 /**
group-Avnet 0:478cfd88041f 1475 * @}
group-Avnet 0:478cfd88041f 1476 */
group-Avnet 0:478cfd88041f 1477
group-Avnet 0:478cfd88041f 1478 /** @defgroup MBUS_CTRL_Register
group-Avnet 0:478cfd88041f 1479 * @{
group-Avnet 0:478cfd88041f 1480 */
group-Avnet 0:478cfd88041f 1481
group-Avnet 0:478cfd88041f 1482 /**
group-Avnet 0:478cfd88041f 1483 * \brief MBUS_CTRL register
group-Avnet 0:478cfd88041f 1484 * \code
group-Avnet 0:478cfd88041f 1485 * Read Write
group-Avnet 0:478cfd88041f 1486 * Default value: 0x00
group-Avnet 0:478cfd88041f 1487 *
group-Avnet 0:478cfd88041f 1488 * 7:4 NOT_USED
group-Avnet 0:478cfd88041f 1489 *
group-Avnet 0:478cfd88041f 1490 * 3:1 MBUS_SUBMODE[2:0]: MBUS submode (allowed values are 0,1,3,5)
group-Avnet 0:478cfd88041f 1491 *
group-Avnet 0:478cfd88041f 1492 * 0 NOT_USED
group-Avnet 0:478cfd88041f 1493 * \endcode
group-Avnet 0:478cfd88041f 1494 */
group-Avnet 0:478cfd88041f 1495 #define MBUS_CTRL_BASE ((uint8_t)0x3D) /*!< MBUS sub-modes (S1, S2 short/long header, T1, T2, R2) */
group-Avnet 0:478cfd88041f 1496
group-Avnet 0:478cfd88041f 1497 #define MBUS_CTRL_MBUS_SUBMODE_S1_S2L ((uint8_t)0x00) /*!< MBUS sub-modes S1 & S2L, header lenght min 279, sync 0x7696, Manchester */
group-Avnet 0:478cfd88041f 1498 #define MBUS_CTRL_MBUS_SUBMODE_S2_S1M_T2_OTHER ((uint8_t)0x02) /*!< MBUS sub-modes S2, S1-m, T2 (only other to meter) short header, header lenght min 15, sync 0x7696, Manchester */
group-Avnet 0:478cfd88041f 1499 #define MBUS_CTRL_MBUS_SUBMODE_T1_T2_METER ((uint8_t)0x06) /*!< MBUS sub-modes T1, T2 (only meter to other), header lenght min 19, sync 0x3D, 3 out of 6 */
group-Avnet 0:478cfd88041f 1500 #define MBUS_CTRL_MBUS_SUBMODE_R2 ((uint8_t)0x0A) /*!< MBUS sub-mode R2, header lenght min 39, sync 0x7696, Manchester */
group-Avnet 0:478cfd88041f 1501
group-Avnet 0:478cfd88041f 1502 /**
group-Avnet 0:478cfd88041f 1503 * @}
group-Avnet 0:478cfd88041f 1504 */
group-Avnet 0:478cfd88041f 1505
group-Avnet 0:478cfd88041f 1506
group-Avnet 0:478cfd88041f 1507
group-Avnet 0:478cfd88041f 1508 /** @defgroup PCKT_FLT_GOALS_CONTROLx_MASK_Registers
group-Avnet 0:478cfd88041f 1509 * @{
group-Avnet 0:478cfd88041f 1510 */
group-Avnet 0:478cfd88041f 1511
group-Avnet 0:478cfd88041f 1512 /**
group-Avnet 0:478cfd88041f 1513 * \brief PCKT_FLT_GOALS_CONTROLx_MASK registers
group-Avnet 0:478cfd88041f 1514 * \code
group-Avnet 0:478cfd88041f 1515 * Default value: 0x00
group-Avnet 0:478cfd88041f 1516 * Read Write
group-Avnet 0:478cfd88041f 1517 * 7:0 CONTROLx_MASK[7:0]: All 0s - no filtering
group-Avnet 0:478cfd88041f 1518 *
group-Avnet 0:478cfd88041f 1519 * \endcode
group-Avnet 0:478cfd88041f 1520 */
group-Avnet 0:478cfd88041f 1521 #define PCKT_FLT_GOALS_CONTROL0_MASK_BASE ((uint8_t)0x42) /*!< Packet control field #3 mask, all 0s -> no filtering */
group-Avnet 0:478cfd88041f 1522
group-Avnet 0:478cfd88041f 1523 #define PCKT_FLT_GOALS_CONTROL1_MASK_BASE ((uint8_t)0x43) /*!< Packet control field #2 mask, all 0s -> no filtering */
group-Avnet 0:478cfd88041f 1524
group-Avnet 0:478cfd88041f 1525 #define PCKT_FLT_GOALS_CONTROL2_MASK_BASE ((uint8_t)0x44) /*!< Packet control field #1 mask, all 0s -> no filtering */
group-Avnet 0:478cfd88041f 1526
group-Avnet 0:478cfd88041f 1527 #define PCKT_FLT_GOALS_CONTROL3_MASK_BASE ((uint8_t)0x45) /*!< Packet control field #0 mask, all 0s -> no filtering */
group-Avnet 0:478cfd88041f 1528
group-Avnet 0:478cfd88041f 1529 /**
group-Avnet 0:478cfd88041f 1530 * @}
group-Avnet 0:478cfd88041f 1531 */
group-Avnet 0:478cfd88041f 1532
group-Avnet 0:478cfd88041f 1533 /** @defgroup PCKT_FLT_GOALS_CONTROLx_FIELD_Registers
group-Avnet 0:478cfd88041f 1534 * @{
group-Avnet 0:478cfd88041f 1535 */
group-Avnet 0:478cfd88041f 1536
group-Avnet 0:478cfd88041f 1537 /**
group-Avnet 0:478cfd88041f 1538 * \brief PCKT_FLT_GOALS_CONTROLx_FIELD registers
group-Avnet 0:478cfd88041f 1539 * \code
group-Avnet 0:478cfd88041f 1540 * Default value: 0x00
group-Avnet 0:478cfd88041f 1541 * Read Write
group-Avnet 0:478cfd88041f 1542 * 7:0 CONTROLx_FIELD[7:0]: Control field (byte x) to be used as reference
group-Avnet 0:478cfd88041f 1543 *
group-Avnet 0:478cfd88041f 1544 * \endcode
group-Avnet 0:478cfd88041f 1545 */
group-Avnet 0:478cfd88041f 1546 #define PCKT_FLT_GOALS_CONTROL0_FIELD_BASE ((uint8_t)0x46) /*!< Control field (byte #3) */
group-Avnet 0:478cfd88041f 1547
group-Avnet 0:478cfd88041f 1548 #define PCKT_FLT_GOALS_CONTROL1_FIELD_BASE ((uint8_t)0x47) /*!< Control field (byte #2) */
group-Avnet 0:478cfd88041f 1549
group-Avnet 0:478cfd88041f 1550 #define PCKT_FLT_GOALS_CONTROL2_FIELD_BASE ((uint8_t)0x48) /*!< Control field (byte #1) */
group-Avnet 0:478cfd88041f 1551
group-Avnet 0:478cfd88041f 1552 #define PCKT_FLT_GOALS_CONTROL3_FIELD_BASE ((uint8_t)0x49) /*!< Control field (byte #0) */
group-Avnet 0:478cfd88041f 1553
group-Avnet 0:478cfd88041f 1554 /**
group-Avnet 0:478cfd88041f 1555 * @}
group-Avnet 0:478cfd88041f 1556 */
group-Avnet 0:478cfd88041f 1557
group-Avnet 0:478cfd88041f 1558 /** @defgroup PCKT_FLT_GOALS_SOURCE_MASK_Register
group-Avnet 0:478cfd88041f 1559 * @{
group-Avnet 0:478cfd88041f 1560 */
group-Avnet 0:478cfd88041f 1561
group-Avnet 0:478cfd88041f 1562 /**
group-Avnet 0:478cfd88041f 1563 * \brief PCKT_FLT_GOALS_SOURCE_MASK register
group-Avnet 0:478cfd88041f 1564 * \code
group-Avnet 0:478cfd88041f 1565 * Default value: 0x00
group-Avnet 0:478cfd88041f 1566 * Read Write
group-Avnet 0:478cfd88041f 1567 * 7:0 RX_SOURCE_MASK[7:0]: For received packet only: all 0s - no filtering
group-Avnet 0:478cfd88041f 1568 *
group-Avnet 0:478cfd88041f 1569 * \endcode
group-Avnet 0:478cfd88041f 1570 */
group-Avnet 0:478cfd88041f 1571 #define PCKT_FLT_GOALS_SOURCE_MASK_BASE ((uint8_t)0x4A) /*!< Source address mask, valid in RX mode */
group-Avnet 0:478cfd88041f 1572
group-Avnet 0:478cfd88041f 1573 /**
group-Avnet 0:478cfd88041f 1574 * @}
group-Avnet 0:478cfd88041f 1575 */
group-Avnet 0:478cfd88041f 1576
group-Avnet 0:478cfd88041f 1577 /** @defgroup PCKT_FLT_GOALS_SOURCE_ADDR_Register
group-Avnet 0:478cfd88041f 1578 * @{
group-Avnet 0:478cfd88041f 1579 */
group-Avnet 0:478cfd88041f 1580 /**
group-Avnet 0:478cfd88041f 1581 * \brief PCKT_FLT_GOALS_SOURCE_ADDR register
group-Avnet 0:478cfd88041f 1582 * \code
group-Avnet 0:478cfd88041f 1583 * Default value: 0x00
group-Avnet 0:478cfd88041f 1584 * Read Write
group-Avnet 0:478cfd88041f 1585 * 7:0 RX_SOURCE_ADDR[7:0]: RX packet source / TX packet destination fields
group-Avnet 0:478cfd88041f 1586 *
group-Avnet 0:478cfd88041f 1587 * \endcode
group-Avnet 0:478cfd88041f 1588 */
group-Avnet 0:478cfd88041f 1589 #define PCKT_FLT_GOALS_SOURCE_ADDR_BASE ((uint8_t)0x4B) /*!< Source address */
group-Avnet 0:478cfd88041f 1590
group-Avnet 0:478cfd88041f 1591 /**
group-Avnet 0:478cfd88041f 1592 * @}
group-Avnet 0:478cfd88041f 1593 */
group-Avnet 0:478cfd88041f 1594
group-Avnet 0:478cfd88041f 1595 /** @defgroup PCKT_FLT_GOALS_BROADCAST_Register
group-Avnet 0:478cfd88041f 1596 * @{
group-Avnet 0:478cfd88041f 1597 */
group-Avnet 0:478cfd88041f 1598
group-Avnet 0:478cfd88041f 1599 /**
group-Avnet 0:478cfd88041f 1600 * \brief PCKT_FLT_GOALS_BROADCAST register
group-Avnet 0:478cfd88041f 1601 * \code
group-Avnet 0:478cfd88041f 1602 * Default value: 0x00
group-Avnet 0:478cfd88041f 1603 * Read Write
group-Avnet 0:478cfd88041f 1604 * 7:0 BROADCAST[7:0]: Address shared for broadcast communication link
group-Avnet 0:478cfd88041f 1605 *
group-Avnet 0:478cfd88041f 1606 * \endcode
group-Avnet 0:478cfd88041f 1607 */
group-Avnet 0:478cfd88041f 1608 #define PCKT_FLT_GOALS_BROADCAST_BASE ((uint8_t)0x4C) /*!< Address shared for broadcast communication links */
group-Avnet 0:478cfd88041f 1609
group-Avnet 0:478cfd88041f 1610 /**
group-Avnet 0:478cfd88041f 1611 * @}
group-Avnet 0:478cfd88041f 1612 */
group-Avnet 0:478cfd88041f 1613
group-Avnet 0:478cfd88041f 1614 /** @defgroup PCKT_FLT_GOALS_MULTICAST_Register
group-Avnet 0:478cfd88041f 1615 * @{
group-Avnet 0:478cfd88041f 1616 */
group-Avnet 0:478cfd88041f 1617
group-Avnet 0:478cfd88041f 1618 /**
group-Avnet 0:478cfd88041f 1619 * \brief PCKT_FLT_GOALS_MULTICAST register
group-Avnet 0:478cfd88041f 1620 * \code
group-Avnet 0:478cfd88041f 1621 * Default value: 0x00
group-Avnet 0:478cfd88041f 1622 * Read Write
group-Avnet 0:478cfd88041f 1623 * 7:0 MULTICAST[7:0]: Address shared for multicast communication links
group-Avnet 0:478cfd88041f 1624 *
group-Avnet 0:478cfd88041f 1625 * \endcode
group-Avnet 0:478cfd88041f 1626 */
group-Avnet 0:478cfd88041f 1627 #define PCKT_FLT_GOALS_MULTICAST_BASE ((uint8_t)0x4D) /*!< Address shared for multicast communication links */
group-Avnet 0:478cfd88041f 1628
group-Avnet 0:478cfd88041f 1629 /**
group-Avnet 0:478cfd88041f 1630 * @}
group-Avnet 0:478cfd88041f 1631 */
group-Avnet 0:478cfd88041f 1632
group-Avnet 0:478cfd88041f 1633 /** @defgroup PCKT_FLT_GOALS_TX_SOURCE_ADDR_Register
group-Avnet 0:478cfd88041f 1634 * @{
group-Avnet 0:478cfd88041f 1635 */
group-Avnet 0:478cfd88041f 1636
group-Avnet 0:478cfd88041f 1637 /**
group-Avnet 0:478cfd88041f 1638 * \brief PCKT_FLT_GOALS_TX_SOURCE_ADDR register
group-Avnet 0:478cfd88041f 1639 * \code
group-Avnet 0:478cfd88041f 1640 * Default value: 0x00
group-Avnet 0:478cfd88041f 1641 * Read Write
group-Avnet 0:478cfd88041f 1642 * 7:0 TX_SOURCE_ADDR[7:0]: TX packet source / RX packet destination fields
group-Avnet 0:478cfd88041f 1643 *
group-Avnet 0:478cfd88041f 1644 * \endcode
group-Avnet 0:478cfd88041f 1645 */
group-Avnet 0:478cfd88041f 1646 #define PCKT_FLT_GOALS_TX_ADDR_BASE ((uint8_t)0x4E) /*!< Address of the destination (also device own address) */
group-Avnet 0:478cfd88041f 1647
group-Avnet 0:478cfd88041f 1648 /**
group-Avnet 0:478cfd88041f 1649 * @}
group-Avnet 0:478cfd88041f 1650 */
group-Avnet 0:478cfd88041f 1651
group-Avnet 0:478cfd88041f 1652 /** @defgroup PCKT_FLT_OPTIONS_Register
group-Avnet 0:478cfd88041f 1653 * @{
group-Avnet 0:478cfd88041f 1654 */
group-Avnet 0:478cfd88041f 1655
group-Avnet 0:478cfd88041f 1656 /**
group-Avnet 0:478cfd88041f 1657 * \brief PCKT_FLT_OPTIONS register
group-Avnet 0:478cfd88041f 1658 * \code
group-Avnet 0:478cfd88041f 1659 * Default value: 0x70
group-Avnet 0:478cfd88041f 1660 * Read Write
group-Avnet 0:478cfd88041f 1661 * 7 Reserved.
group-Avnet 0:478cfd88041f 1662 *
group-Avnet 0:478cfd88041f 1663 * 6 RX_TIMEOUT_AND_OR_SELECT[0]: 1 - ‘OR’ logical function applied to CS/SQI/PQI
group-Avnet 0:478cfd88041f 1664 * values (masked by 7:5 bits in PROTOCOL register)
group-Avnet 0:478cfd88041f 1665 * 5 CONTROL_FILTERING[0]: 1 - RX packet accepted if its control fields matches
group-Avnet 0:478cfd88041f 1666 * with masked CONTROLx_FIELD registers.
group-Avnet 0:478cfd88041f 1667 * 4 SOURCE_FILTERING[0]: 1 - RX packet accepted if its source field
group-Avnet 0:478cfd88041f 1668 * matches w/ masked RX_SOURCE_ADDR register.
group-Avnet 0:478cfd88041f 1669 * 3 DEST_VS_ SOURCE _ADDR[0]: 1 - RX packet accepted if its destination
group-Avnet 0:478cfd88041f 1670 * address matches with TX_SOURCE_ADDR reg.
group-Avnet 0:478cfd88041f 1671 * 2 DEST_VS_MULTICAST_ADDR[0]: 1 - RX packet accepted if its destination
group-Avnet 0:478cfd88041f 1672 * address matches with MULTICAST register
group-Avnet 0:478cfd88041f 1673 * 1 DEST_VS_BROADCAST_ADDR[0]: 1 - RX packet accepted if its destination
group-Avnet 0:478cfd88041f 1674 * address matches with BROADCAST register.
group-Avnet 0:478cfd88041f 1675 * 0 CRC_CHECK[0]: 1 - packet discarded if CRC not valid.
group-Avnet 0:478cfd88041f 1676 *
group-Avnet 0:478cfd88041f 1677 * \endcode
group-Avnet 0:478cfd88041f 1678 */
group-Avnet 0:478cfd88041f 1679 #define PCKT_FLT_OPTIONS_BASE ((uint8_t)0x4F) /*!< Options relative to packet filtering */
group-Avnet 0:478cfd88041f 1680
group-Avnet 0:478cfd88041f 1681 #define PCKT_FLT_OPTIONS_CRC_CHECK_MASK ((uint8_t)0x01) /*!< Enable/disable of CRC check: packet is discarded if CRC is not valid [RX] */
group-Avnet 0:478cfd88041f 1682 #define PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK ((uint8_t)0x02) /*!< Packet discarded if destination address differs from BROADCAST register [RX] */
group-Avnet 0:478cfd88041f 1683 #define PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK ((uint8_t)0x04) /*!< Packet discarded if destination address differs from MULTICAST register [RX] */
group-Avnet 0:478cfd88041f 1684 #define PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK ((uint8_t)0x08) /*!< Packet discarded if destination address differs from TX_ADDR register [RX] */
group-Avnet 0:478cfd88041f 1685 #define PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK ((uint8_t)0x10) /*!< Packet discarded if source address (masked by the SOURCE_MASK register)
group-Avnet 0:478cfd88041f 1686 differs from SOURCE_ADDR register [RX] */
group-Avnet 0:478cfd88041f 1687 #define PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK ((uint8_t)0x20) /*!< Packet discarded if the x-byte (x=1¸4) control field (masked by the CONTROLx_MASK register)
group-Avnet 0:478cfd88041f 1688 differs from CONTROLx_FIELD register [RX] */
group-Avnet 0:478cfd88041f 1689 #define PCKT_FLT_OPTIONS_RX_TIMEOUT_AND_OR_SELECT ((uint8_t)0x40) /*!< Logical function applied to CS/SQI/PQI values (masked by [7:5] bits in PROTOCOL[2]
group-Avnet 0:478cfd88041f 1690 register) */
group-Avnet 0:478cfd88041f 1691
group-Avnet 0:478cfd88041f 1692 /**
group-Avnet 0:478cfd88041f 1693 * @}
group-Avnet 0:478cfd88041f 1694 */
group-Avnet 0:478cfd88041f 1695
group-Avnet 0:478cfd88041f 1696 /** @defgroup TX_CTRL_FIELD_Registers
group-Avnet 0:478cfd88041f 1697 * @{
group-Avnet 0:478cfd88041f 1698 */
group-Avnet 0:478cfd88041f 1699
group-Avnet 0:478cfd88041f 1700 /**
group-Avnet 0:478cfd88041f 1701 * \brief TX_CTRL_FIELDx registers
group-Avnet 0:478cfd88041f 1702 * \code
group-Avnet 0:478cfd88041f 1703 * Default value: 0x00
group-Avnet 0:478cfd88041f 1704 * Read Write
group-Avnet 0:478cfd88041f 1705 * 7:0 TX_CTRLx[7:0]: Control field value to be used in TX packet as byte n.x
group-Avnet 0:478cfd88041f 1706 * \endcode
group-Avnet 0:478cfd88041f 1707 */
group-Avnet 0:478cfd88041f 1708 #define TX_CTRL_FIELD3_BASE ((uint8_t)0x68) /*!< Control field value to be used in TX packet as byte n.3 */
group-Avnet 0:478cfd88041f 1709
group-Avnet 0:478cfd88041f 1710 #define TX_CTRL_FIELD2_BASE ((uint8_t)0x69) /*!< Control field value to be used in TX packet as byte n.2 */
group-Avnet 0:478cfd88041f 1711
group-Avnet 0:478cfd88041f 1712 #define TX_CTRL_FIELD1_BASE ((uint8_t)0x6A) /*!< Control field value to be used in TX packet as byte n.1 */
group-Avnet 0:478cfd88041f 1713
group-Avnet 0:478cfd88041f 1714 #define TX_CTRL_FIELD0_BASE ((uint8_t)0x6B) /*!< Control field value to be used in TX packet as byte n.0 */
group-Avnet 0:478cfd88041f 1715
group-Avnet 0:478cfd88041f 1716 /**
group-Avnet 0:478cfd88041f 1717 * @}
group-Avnet 0:478cfd88041f 1718 */
group-Avnet 0:478cfd88041f 1719
group-Avnet 0:478cfd88041f 1720
group-Avnet 0:478cfd88041f 1721 /** @defgroup TX_PCKT_INFO_Register
group-Avnet 0:478cfd88041f 1722 * @{
group-Avnet 0:478cfd88041f 1723 */
group-Avnet 0:478cfd88041f 1724
group-Avnet 0:478cfd88041f 1725 /**
group-Avnet 0:478cfd88041f 1726 * \brief TX_PCKT_INFO registers
group-Avnet 0:478cfd88041f 1727 * \code
group-Avnet 0:478cfd88041f 1728 * Default value: 0x00
group-Avnet 0:478cfd88041f 1729 * Read
group-Avnet 0:478cfd88041f 1730 *
group-Avnet 0:478cfd88041f 1731 * 7:6 Not used.
group-Avnet 0:478cfd88041f 1732 *
group-Avnet 0:478cfd88041f 1733 * 5:4 TX_SEQ_NUM: Current TX packet sequence number
group-Avnet 0:478cfd88041f 1734 *
group-Avnet 0:478cfd88041f 1735 * 0 N_RETX[3:0]: Number of retransmissions done on the
group-Avnet 0:478cfd88041f 1736 * last TX packet
group-Avnet 0:478cfd88041f 1737 * \endcode
group-Avnet 0:478cfd88041f 1738 */
group-Avnet 0:478cfd88041f 1739 #define TX_PCKT_INFO_BASE ((uint8_t)(0xC2)) /*!< Current TX packet sequence number [5:4];
group-Avnet 0:478cfd88041f 1740 Number of retransmissions done on the last TX packet [3:0]*/
group-Avnet 0:478cfd88041f 1741 /**
group-Avnet 0:478cfd88041f 1742 * @}
group-Avnet 0:478cfd88041f 1743 */
group-Avnet 0:478cfd88041f 1744
group-Avnet 0:478cfd88041f 1745 /** @defgroup RX_PCKT_INFO_Register
group-Avnet 0:478cfd88041f 1746 * @{
group-Avnet 0:478cfd88041f 1747 */
group-Avnet 0:478cfd88041f 1748
group-Avnet 0:478cfd88041f 1749 /**
group-Avnet 0:478cfd88041f 1750 * \brief RX_PCKT_INFO registers
group-Avnet 0:478cfd88041f 1751 * \code
group-Avnet 0:478cfd88041f 1752 * Default value: 0x00
group-Avnet 0:478cfd88041f 1753 * Read
group-Avnet 0:478cfd88041f 1754 *
group-Avnet 0:478cfd88041f 1755 * 7:3 Not used.
group-Avnet 0:478cfd88041f 1756 *
group-Avnet 0:478cfd88041f 1757 * 2 NACK_RX: NACK field of the received packet
group-Avnet 0:478cfd88041f 1758 *
group-Avnet 0:478cfd88041f 1759 * 1:0 RX_SEQ_NUM[1:0]: Sequence number of the received packet
group-Avnet 0:478cfd88041f 1760 * \endcode
group-Avnet 0:478cfd88041f 1761 */
group-Avnet 0:478cfd88041f 1762 #define RX_PCKT_INFO_BASE ((uint8_t)(0xC3)) /*!< NO_ACK field of the received packet [2];
group-Avnet 0:478cfd88041f 1763 sequence number of the received packet [1:0]*/
group-Avnet 0:478cfd88041f 1764
group-Avnet 0:478cfd88041f 1765 #define TX_PCKT_INFO_NACK_RX ((uint8_t)(0x04)) /*!< NACK field of the received packet */
group-Avnet 0:478cfd88041f 1766
group-Avnet 0:478cfd88041f 1767 /**
group-Avnet 0:478cfd88041f 1768 * @}
group-Avnet 0:478cfd88041f 1769 */
group-Avnet 0:478cfd88041f 1770
group-Avnet 0:478cfd88041f 1771 /** @defgroup RX_PCKT_LEN1
group-Avnet 0:478cfd88041f 1772 * @{
group-Avnet 0:478cfd88041f 1773 */
group-Avnet 0:478cfd88041f 1774
group-Avnet 0:478cfd88041f 1775 /**
group-Avnet 0:478cfd88041f 1776 * \brief RX_PCKT_LEN1 registers
group-Avnet 0:478cfd88041f 1777 * \code
group-Avnet 0:478cfd88041f 1778 * Default value: 0x00
group-Avnet 0:478cfd88041f 1779 * Read
group-Avnet 0:478cfd88041f 1780 *
group-Avnet 0:478cfd88041f 1781 * 7:0 RX_PCKT_LEN1[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0
group-Avnet 0:478cfd88041f 1782 * This value is packet_length/256
group-Avnet 0:478cfd88041f 1783 * \endcode
group-Avnet 0:478cfd88041f 1784 */
group-Avnet 0:478cfd88041f 1785 #define RX_PCKT_LEN1_BASE ((uint8_t)(0xC9)) /*!< Length (number of bytes) of the received packet: */
group-Avnet 0:478cfd88041f 1786
group-Avnet 0:478cfd88041f 1787 /**
group-Avnet 0:478cfd88041f 1788 * @}
group-Avnet 0:478cfd88041f 1789 */
group-Avnet 0:478cfd88041f 1790
group-Avnet 0:478cfd88041f 1791 /** @defgroup RX_PCKT_LEN0
group-Avnet 0:478cfd88041f 1792 * @{
group-Avnet 0:478cfd88041f 1793 */
group-Avnet 0:478cfd88041f 1794
group-Avnet 0:478cfd88041f 1795 /**
group-Avnet 0:478cfd88041f 1796 * \brief RX_PCKT_LEN0 registers
group-Avnet 0:478cfd88041f 1797 * \code
group-Avnet 0:478cfd88041f 1798 * Default value: 0x00
group-Avnet 0:478cfd88041f 1799 * Read
group-Avnet 0:478cfd88041f 1800 *
group-Avnet 0:478cfd88041f 1801 * 7:0 RX_PCKT_LEN0[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0
group-Avnet 0:478cfd88041f 1802 * This value is packet_length%256
group-Avnet 0:478cfd88041f 1803 * \endcode
group-Avnet 0:478cfd88041f 1804 */
group-Avnet 0:478cfd88041f 1805 #define RX_PCKT_LEN0_BASE ((uint8_t)(0xCA)) /*!< RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 */
group-Avnet 0:478cfd88041f 1806
group-Avnet 0:478cfd88041f 1807 /**
group-Avnet 0:478cfd88041f 1808 * @}
group-Avnet 0:478cfd88041f 1809 */
group-Avnet 0:478cfd88041f 1810
group-Avnet 0:478cfd88041f 1811
group-Avnet 0:478cfd88041f 1812 /** @defgroup CRC_FIELD_Register
group-Avnet 0:478cfd88041f 1813 * @{
group-Avnet 0:478cfd88041f 1814 */
group-Avnet 0:478cfd88041f 1815
group-Avnet 0:478cfd88041f 1816 /**
group-Avnet 0:478cfd88041f 1817 * \brief CRC_FIELD[2:0] registers
group-Avnet 0:478cfd88041f 1818 * \code
group-Avnet 0:478cfd88041f 1819 * Default value: 0x00
group-Avnet 0:478cfd88041f 1820 * Read
group-Avnet 0:478cfd88041f 1821 *
group-Avnet 0:478cfd88041f 1822 * 7:0 CRC_FIELDx[7:0]: upper(x=2), middle(x=1) and lower(x=0) part of the crc field of the received packet
group-Avnet 0:478cfd88041f 1823 * \endcode
group-Avnet 0:478cfd88041f 1824 */
group-Avnet 0:478cfd88041f 1825 #define CRC_FIELD2_BASE ((uint8_t)(0xCB)) /*!< CRC2 field of the received packet */
group-Avnet 0:478cfd88041f 1826
group-Avnet 0:478cfd88041f 1827 #define CRC_FIELD1_BASE ((uint8_t)(0xCC)) /*!< CRC1 field of the received packet */
group-Avnet 0:478cfd88041f 1828
group-Avnet 0:478cfd88041f 1829 #define CRC_FIELD0_BASE ((uint8_t)(0xCD)) /*!< CRC0 field of the received packet */
group-Avnet 0:478cfd88041f 1830
group-Avnet 0:478cfd88041f 1831 /**
group-Avnet 0:478cfd88041f 1832 * @}
group-Avnet 0:478cfd88041f 1833 */
group-Avnet 0:478cfd88041f 1834
group-Avnet 0:478cfd88041f 1835 /** @defgroup RX_CTRL_FIELD_Register
group-Avnet 0:478cfd88041f 1836 * @{
group-Avnet 0:478cfd88041f 1837 */
group-Avnet 0:478cfd88041f 1838
group-Avnet 0:478cfd88041f 1839 /**
group-Avnet 0:478cfd88041f 1840 * \brief RX_CTRL_FIELD[3:0] registers
group-Avnet 0:478cfd88041f 1841 * \code
group-Avnet 0:478cfd88041f 1842 * Default value: 0x00
group-Avnet 0:478cfd88041f 1843 * Read
group-Avnet 0:478cfd88041f 1844 *
group-Avnet 0:478cfd88041f 1845 * 7:0 RX_CTRL_FIELDx[7:0]: upper(x=3), middle(x=2), middle(x=1) and lower(x=0) part of the control field of the received packet
group-Avnet 0:478cfd88041f 1846 * \endcode
group-Avnet 0:478cfd88041f 1847 */
group-Avnet 0:478cfd88041f 1848 #define RX_CTRL_FIELD0_BASE ((uint8_t)(0xCE)) /*!< CRTL3 Control field of the received packet */
group-Avnet 0:478cfd88041f 1849
group-Avnet 0:478cfd88041f 1850 #define RX_CTRL_FIELD1_BASE ((uint8_t)(0xCF)) /*!< CRTL2 Control field of the received packet */
group-Avnet 0:478cfd88041f 1851
group-Avnet 0:478cfd88041f 1852 #define RX_CTRL_FIELD2_BASE ((uint8_t)(0xD0)) /*!< CRTL1 Control field of the received packet */
group-Avnet 0:478cfd88041f 1853
group-Avnet 0:478cfd88041f 1854 #define RX_CTRL_FIELD3_BASE ((uint8_t)(0xD1)) /*!< CRTL0 Control field of the received packet */
group-Avnet 0:478cfd88041f 1855
group-Avnet 0:478cfd88041f 1856 /**
group-Avnet 0:478cfd88041f 1857 * @}
group-Avnet 0:478cfd88041f 1858 */
group-Avnet 0:478cfd88041f 1859
group-Avnet 0:478cfd88041f 1860 /** @defgroup RX_ADDR_FIELD_Register
group-Avnet 0:478cfd88041f 1861 * @{
group-Avnet 0:478cfd88041f 1862 */
group-Avnet 0:478cfd88041f 1863
group-Avnet 0:478cfd88041f 1864 /**
group-Avnet 0:478cfd88041f 1865 * \brief RX_ADDR_FIELD[1:0] registers
group-Avnet 0:478cfd88041f 1866 * \code
group-Avnet 0:478cfd88041f 1867 * Default value: 0x00
group-Avnet 0:478cfd88041f 1868 * Read
group-Avnet 0:478cfd88041f 1869 *
group-Avnet 0:478cfd88041f 1870 * 7:0 RX_ADDR_FIELDx[7:0]: source(x=1) and destination(x=0) address field of the received packet
group-Avnet 0:478cfd88041f 1871 * \endcode
group-Avnet 0:478cfd88041f 1872 */
group-Avnet 0:478cfd88041f 1873 #define RX_ADDR_FIELD1_BASE ((uint8_t)(0xD2)) /*!< ADDR1 Address field of the received packet */
group-Avnet 0:478cfd88041f 1874
group-Avnet 0:478cfd88041f 1875 #define RX_ADDR_FIELD0_BASE ((uint8_t)(0xD3)) /*!< ADDR0 Address field of the received packet */
group-Avnet 0:478cfd88041f 1876
group-Avnet 0:478cfd88041f 1877 /**
group-Avnet 0:478cfd88041f 1878 * @}
group-Avnet 0:478cfd88041f 1879 */
group-Avnet 0:478cfd88041f 1880
group-Avnet 0:478cfd88041f 1881 /**
group-Avnet 0:478cfd88041f 1882 * @}
group-Avnet 0:478cfd88041f 1883 */
group-Avnet 0:478cfd88041f 1884
group-Avnet 0:478cfd88041f 1885
group-Avnet 0:478cfd88041f 1886 /** @defgroup Protocol_Registers
group-Avnet 0:478cfd88041f 1887 * @{
group-Avnet 0:478cfd88041f 1888 */
group-Avnet 0:478cfd88041f 1889
group-Avnet 0:478cfd88041f 1890 /** @defgroup PROTOCOL2_Register
group-Avnet 0:478cfd88041f 1891 * @{
group-Avnet 0:478cfd88041f 1892 */
group-Avnet 0:478cfd88041f 1893
group-Avnet 0:478cfd88041f 1894 /**
group-Avnet 0:478cfd88041f 1895 * \brief PROTOCOL2 register
group-Avnet 0:478cfd88041f 1896 * \code
group-Avnet 0:478cfd88041f 1897 * Default value: 0x06
group-Avnet 0:478cfd88041f 1898 * Read Write
group-Avnet 0:478cfd88041f 1899 * 7 CS_TIMEOUT_MASK: 1 - CS value contributes to timeout disabling
group-Avnet 0:478cfd88041f 1900 *
group-Avnet 0:478cfd88041f 1901 * 6 SQI_TIMEOUT_MASK: 1 - SQI value contributes to timeout disabling
group-Avnet 0:478cfd88041f 1902 *
group-Avnet 0:478cfd88041f 1903 * 5 PQI_TIMEOUT_MASK: 1 - PQI value contributes to timeout disabling
group-Avnet 0:478cfd88041f 1904 *
group-Avnet 0:478cfd88041f 1905 * 4:3 TX_SEQ_NUM_RELOAD[1:0]: TX sequence number to be used when counting reset is required using the related command.
group-Avnet 0:478cfd88041f 1906 *
group-Avnet 0:478cfd88041f 1907 * 2 RCO_CALIBRATION[0]: 1 - Enables the automatic RCO calibration
group-Avnet 0:478cfd88041f 1908 *
group-Avnet 0:478cfd88041f 1909 * 1 VCO_CALIBRATION[0]: 1 - Enables the automatic VCO calibration
group-Avnet 0:478cfd88041f 1910 *
group-Avnet 0:478cfd88041f 1911 * 0 LDCR_MODE[0]: 1 - LDCR mode enabled
group-Avnet 0:478cfd88041f 1912 *
group-Avnet 0:478cfd88041f 1913 * \endcode
group-Avnet 0:478cfd88041f 1914 */
group-Avnet 0:478cfd88041f 1915 #define PROTOCOL2_BASE ((uint8_t)0x50) /*!< Protocol2 regisetr address */
group-Avnet 0:478cfd88041f 1916
group-Avnet 0:478cfd88041f 1917 #define PROTOCOL2_LDC_MODE_MASK ((uint8_t)0x01) /*!< Enable/disable Low duty Cycle mode */
group-Avnet 0:478cfd88041f 1918 #define PROTOCOL2_VCO_CALIBRATION_MASK ((uint8_t)0x02) /*!< Enable/disable VCO automatic calibration */
group-Avnet 0:478cfd88041f 1919 #define PROTOCOL2_RCO_CALIBRATION_MASK ((uint8_t)0x04) /*!< Enable/disable RCO automatic calibration */
group-Avnet 0:478cfd88041f 1920 #define PROTOCOL2_PQI_TIMEOUT_MASK ((uint8_t)0x20) /*!< PQI value contributes to timeout disabling */
group-Avnet 0:478cfd88041f 1921 #define PROTOCOL2_SQI_TIMEOUT_MASK ((uint8_t)0x40) /*!< SQI value contributes to timeout disabling */
group-Avnet 0:478cfd88041f 1922 #define PROTOCOL2_CS_TIMEOUT_MASK ((uint8_t)0x80) /*!< CS value contributes to timeout disabling */
group-Avnet 0:478cfd88041f 1923
group-Avnet 0:478cfd88041f 1924 /**
group-Avnet 0:478cfd88041f 1925 * @}
group-Avnet 0:478cfd88041f 1926 */
group-Avnet 0:478cfd88041f 1927
group-Avnet 0:478cfd88041f 1928 /** @defgroup PROTOCOL1_Register
group-Avnet 0:478cfd88041f 1929 * @{
group-Avnet 0:478cfd88041f 1930 */
group-Avnet 0:478cfd88041f 1931
group-Avnet 0:478cfd88041f 1932 /**
group-Avnet 0:478cfd88041f 1933 * \brief PROTOCOL1 register
group-Avnet 0:478cfd88041f 1934 * \code
group-Avnet 0:478cfd88041f 1935 * Default value: 0x00
group-Avnet 0:478cfd88041f 1936 * Read Write
group-Avnet 0:478cfd88041f 1937 * 7 LDCR_RELOAD_ON_SYNC: 1 - LDCR timer will be reloaded with the value stored in the LDCR_RELOAD registers
group-Avnet 0:478cfd88041f 1938 *
group-Avnet 0:478cfd88041f 1939 * 6 PIGGYBACKING: 1 - PIGGYBACKING enabled
group-Avnet 0:478cfd88041f 1940 *
group-Avnet 0:478cfd88041f 1941 * 5:4 Reserved.
group-Avnet 0:478cfd88041f 1942 *
group-Avnet 0:478cfd88041f 1943 * 3 SEED_RELOAD[0]: 1 - Reload the back-off random generator
group-Avnet 0:478cfd88041f 1944 * seed using the value written in the
group-Avnet 0:478cfd88041f 1945 * BU_COUNTER_SEED_MSByte / LSByte registers
group-Avnet 0:478cfd88041f 1946 *
group-Avnet 0:478cfd88041f 1947 * 2 CSMA_ON [0]: 1 - CSMA channel access mode enabled
group-Avnet 0:478cfd88041f 1948 *
group-Avnet 0:478cfd88041f 1949 * 1 CSMA_PERS_ON[0]: 1 - CSMA persistent (no back-off) enabled
group-Avnet 0:478cfd88041f 1950 *
group-Avnet 0:478cfd88041f 1951 * 0 AUTO_PCKT_FLT[0]: 1 - automatic packet filtering mode enabled
group-Avnet 0:478cfd88041f 1952 *
group-Avnet 0:478cfd88041f 1953 * \endcode
group-Avnet 0:478cfd88041f 1954 */
group-Avnet 0:478cfd88041f 1955 #define PROTOCOL1_BASE ((uint8_t)0x51) /*!< Protocol1 regisetr address */
group-Avnet 0:478cfd88041f 1956
group-Avnet 0:478cfd88041f 1957 #define PROTOCOL1_AUTO_PCKT_FLT_MASK ((uint8_t)0x01) /*!< Enable/disable automatic packet filtering mode */
group-Avnet 0:478cfd88041f 1958 #define PROTOCOL1_CSMA_PERS_ON_MASK ((uint8_t)0x02) /*!< Enable/disable CSMA persistent (no back-off) */
group-Avnet 0:478cfd88041f 1959 #define PROTOCOL1_CSMA_ON_MASK ((uint8_t)0x04) /*!< Enable/disable CSMA channel access mode */
group-Avnet 0:478cfd88041f 1960 #define PROTOCOL1_SEED_RELOAD_MASK ((uint8_t)0x08) /*!< Reloads the seed of the PN generator for CSMA procedure */
group-Avnet 0:478cfd88041f 1961 #define PROTOCOL1_PIGGYBACKING_MASK ((uint8_t)0x40) /*!< Enable/disable Piggybacking */
group-Avnet 0:478cfd88041f 1962 #define PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK ((uint8_t)0x80) /*!< LDC timer will be reloaded with the value stored in the LDC_RELOAD registers */
group-Avnet 0:478cfd88041f 1963
group-Avnet 0:478cfd88041f 1964 /**
group-Avnet 0:478cfd88041f 1965 * @}
group-Avnet 0:478cfd88041f 1966 */
group-Avnet 0:478cfd88041f 1967
group-Avnet 0:478cfd88041f 1968 /** @defgroup PROTOCOL0_Register
group-Avnet 0:478cfd88041f 1969 * @{
group-Avnet 0:478cfd88041f 1970 */
group-Avnet 0:478cfd88041f 1971
group-Avnet 0:478cfd88041f 1972 /**
group-Avnet 0:478cfd88041f 1973 * \brief PROTOCOL0 register
group-Avnet 0:478cfd88041f 1974 * \code
group-Avnet 0:478cfd88041f 1975 * Default value: 0x08
group-Avnet 0:478cfd88041f 1976 * Read Write
group-Avnet 0:478cfd88041f 1977 * 7:4 NMAX_RETX[3:0]: Max number of re-TX. 0 - re-transmission is not performed
group-Avnet 0:478cfd88041f 1978 *
group-Avnet 0:478cfd88041f 1979 * 3 NACK_TX[0]: 1 - field NO_ACK=1 on transmitted packet
group-Avnet 0:478cfd88041f 1980 *
group-Avnet 0:478cfd88041f 1981 * 2 AUTO_ACK[0]: 1 - automatic ack after RX
group-Avnet 0:478cfd88041f 1982 *
group-Avnet 0:478cfd88041f 1983 * 1 PERS_RX[0]: 1 - persistent reception enabled
group-Avnet 0:478cfd88041f 1984 *
group-Avnet 0:478cfd88041f 1985 * 0 PERS_TX[0]: 1 - persistent transmission enabled
group-Avnet 0:478cfd88041f 1986 *
group-Avnet 0:478cfd88041f 1987 * \endcode
group-Avnet 0:478cfd88041f 1988 */
group-Avnet 0:478cfd88041f 1989 #define PROTOCOL0_BASE ((uint8_t)0x52) /*!< Persistent RX/TX, autoack, Max number of retransmissions */
group-Avnet 0:478cfd88041f 1990
group-Avnet 0:478cfd88041f 1991 #define PROTOCOL0_PERS_TX_MASK ((uint8_t)0x01) /*!< Enables persistent transmission */
group-Avnet 0:478cfd88041f 1992 #define PROTOCOL0_PERS_RX_MASK ((uint8_t)0x02) /*!< Enables persistent reception */
group-Avnet 0:478cfd88041f 1993 #define PROTOCOL0_AUTO_ACK_MASK ((uint8_t)0x04) /*!< Enables auto acknowlegment */
group-Avnet 0:478cfd88041f 1994 #define PROTOCOL0_NACK_TX_MASK ((uint8_t)0x08) /*!< Writes field NO_ACK=1 on transmitted packet */
group-Avnet 0:478cfd88041f 1995 #define PROTOCOL0_NMAX_RETX_MASK ((uint8_t)0xF0) /*!< Retransmission mask */
group-Avnet 0:478cfd88041f 1996
group-Avnet 0:478cfd88041f 1997 /**
group-Avnet 0:478cfd88041f 1998 * @}
group-Avnet 0:478cfd88041f 1999 */
group-Avnet 0:478cfd88041f 2000
group-Avnet 0:478cfd88041f 2001 /** @defgroup TIMERS5_Register
group-Avnet 0:478cfd88041f 2002 * @{
group-Avnet 0:478cfd88041f 2003 */
group-Avnet 0:478cfd88041f 2004
group-Avnet 0:478cfd88041f 2005 /**
group-Avnet 0:478cfd88041f 2006 * \brief TIMERS5 register
group-Avnet 0:478cfd88041f 2007 * \code
group-Avnet 0:478cfd88041f 2008 * Default value: 0x00
group-Avnet 0:478cfd88041f 2009 * Read Write
group-Avnet 0:478cfd88041f 2010 * 7:0 RX_TIMEOUT_PRESCALER[7:0] : RX operation timeout: prescaler value
group-Avnet 0:478cfd88041f 2011 * \endcode
group-Avnet 0:478cfd88041f 2012 */
group-Avnet 0:478cfd88041f 2013 #define TIMERS5_RX_TIMEOUT_PRESCALER_BASE ((uint8_t)0x53) /*!< RX operation timeout: prescaler value */
group-Avnet 0:478cfd88041f 2014
group-Avnet 0:478cfd88041f 2015 /**
group-Avnet 0:478cfd88041f 2016 * @}
group-Avnet 0:478cfd88041f 2017 */
group-Avnet 0:478cfd88041f 2018
group-Avnet 0:478cfd88041f 2019 /** @defgroup TIMERS4_Register
group-Avnet 0:478cfd88041f 2020 * @{
group-Avnet 0:478cfd88041f 2021 */
group-Avnet 0:478cfd88041f 2022
group-Avnet 0:478cfd88041f 2023 /**
group-Avnet 0:478cfd88041f 2024 * \brief TIMERS4 register
group-Avnet 0:478cfd88041f 2025 * \code
group-Avnet 0:478cfd88041f 2026 * Default value: 0x00
group-Avnet 0:478cfd88041f 2027 * Read Write
group-Avnet 0:478cfd88041f 2028 * 7:0 RX_TIMEOUT_COUNTER[7:0] : RX operation timeout: counter value
group-Avnet 0:478cfd88041f 2029 * \endcode
group-Avnet 0:478cfd88041f 2030 */
group-Avnet 0:478cfd88041f 2031 #define TIMERS4_RX_TIMEOUT_COUNTER_BASE ((uint8_t)0x54) /*!< RX operation timeout: counter value */
group-Avnet 0:478cfd88041f 2032
group-Avnet 0:478cfd88041f 2033 /**
group-Avnet 0:478cfd88041f 2034 * @}
group-Avnet 0:478cfd88041f 2035 */
group-Avnet 0:478cfd88041f 2036
group-Avnet 0:478cfd88041f 2037 /** @defgroup TIMERS3_Register
group-Avnet 0:478cfd88041f 2038 * @{
group-Avnet 0:478cfd88041f 2039 */
group-Avnet 0:478cfd88041f 2040
group-Avnet 0:478cfd88041f 2041 /**
group-Avnet 0:478cfd88041f 2042 * \brief TIMERS3 register
group-Avnet 0:478cfd88041f 2043 * \code
group-Avnet 0:478cfd88041f 2044 * Default value: 0x00
group-Avnet 0:478cfd88041f 2045 * Read Write
group-Avnet 0:478cfd88041f 2046 * 7:0 LDCR_PRESCALER[7:0] : LDC Mode: Prescaler part of the wake-up value
group-Avnet 0:478cfd88041f 2047 * \endcode
group-Avnet 0:478cfd88041f 2048 */
group-Avnet 0:478cfd88041f 2049 #define TIMERS3_LDC_PRESCALER_BASE ((uint8_t)0x55) /*!< LDC Mode: Prescaler of the wake-up timer */
group-Avnet 0:478cfd88041f 2050
group-Avnet 0:478cfd88041f 2051 /**
group-Avnet 0:478cfd88041f 2052 * @}
group-Avnet 0:478cfd88041f 2053 */
group-Avnet 0:478cfd88041f 2054
group-Avnet 0:478cfd88041f 2055 /** @defgroup TIMERS2_Register
group-Avnet 0:478cfd88041f 2056 * @{
group-Avnet 0:478cfd88041f 2057 */
group-Avnet 0:478cfd88041f 2058
group-Avnet 0:478cfd88041f 2059 /**
group-Avnet 0:478cfd88041f 2060 * \brief TIMERS2 register
group-Avnet 0:478cfd88041f 2061 * \code
group-Avnet 0:478cfd88041f 2062 * Default value: 0x00
group-Avnet 0:478cfd88041f 2063 * Read Write
group-Avnet 0:478cfd88041f 2064 * 7:0 LDCR_COUNTER[7:0] : LDC Mode: counter part of the wake-up value
group-Avnet 0:478cfd88041f 2065 * \endcode
group-Avnet 0:478cfd88041f 2066 */
group-Avnet 0:478cfd88041f 2067 #define TIMERS2_LDC_COUNTER_BASE ((uint8_t)0x56) /*!< LDC Mode: counter of the wake-up timer */
group-Avnet 0:478cfd88041f 2068
group-Avnet 0:478cfd88041f 2069 /**
group-Avnet 0:478cfd88041f 2070 * @}
group-Avnet 0:478cfd88041f 2071 */
group-Avnet 0:478cfd88041f 2072
group-Avnet 0:478cfd88041f 2073 /** @defgroup TIMERS1_Register
group-Avnet 0:478cfd88041f 2074 * @{
group-Avnet 0:478cfd88041f 2075 */
group-Avnet 0:478cfd88041f 2076
group-Avnet 0:478cfd88041f 2077 /**
group-Avnet 0:478cfd88041f 2078 * \brief TIMERS1 register
group-Avnet 0:478cfd88041f 2079 * \code
group-Avnet 0:478cfd88041f 2080 * Default value: 0x00
group-Avnet 0:478cfd88041f 2081 * Read Write
group-Avnet 0:478cfd88041f 2082 * 7:0 LDCR_RELOAD_PRESCALER[7:0] : LDC Mode: Prescaler part of the reload value
group-Avnet 0:478cfd88041f 2083 * \endcode
group-Avnet 0:478cfd88041f 2084 */
group-Avnet 0:478cfd88041f 2085 #define TIMERS1_LDC_RELOAD_PRESCALER_BASE ((uint8_t)0x57) /*!< LDC Mode: Prescaler part of the reload value */
group-Avnet 0:478cfd88041f 2086
group-Avnet 0:478cfd88041f 2087 /**
group-Avnet 0:478cfd88041f 2088 * @}
group-Avnet 0:478cfd88041f 2089 */
group-Avnet 0:478cfd88041f 2090
group-Avnet 0:478cfd88041f 2091 /** @defgroup TIMERS0_Register
group-Avnet 0:478cfd88041f 2092 * @{
group-Avnet 0:478cfd88041f 2093 */
group-Avnet 0:478cfd88041f 2094
group-Avnet 0:478cfd88041f 2095 /**
group-Avnet 0:478cfd88041f 2096 * \brief TIMERS0 register
group-Avnet 0:478cfd88041f 2097 * \code
group-Avnet 0:478cfd88041f 2098 * Default value: 0x00
group-Avnet 0:478cfd88041f 2099 * Read Write
group-Avnet 0:478cfd88041f 2100 * 7:0 LDCR_RELOAD_COUNTER[7:0] : LDC Mode: Counter part of the reload value
group-Avnet 0:478cfd88041f 2101 * \endcode
group-Avnet 0:478cfd88041f 2102 */
group-Avnet 0:478cfd88041f 2103 #define TIMERS0_LDC_RELOAD_COUNTER_BASE ((uint8_t)0x58) /*!< LDC Mode: Counter part of the reload value */
group-Avnet 0:478cfd88041f 2104
group-Avnet 0:478cfd88041f 2105 /**
group-Avnet 0:478cfd88041f 2106 * @}
group-Avnet 0:478cfd88041f 2107 */
group-Avnet 0:478cfd88041f 2108
group-Avnet 0:478cfd88041f 2109
group-Avnet 0:478cfd88041f 2110 /** @defgroup CSMA_CONFIG3_Register
group-Avnet 0:478cfd88041f 2111 * @{
group-Avnet 0:478cfd88041f 2112 */
group-Avnet 0:478cfd88041f 2113
group-Avnet 0:478cfd88041f 2114 /**
group-Avnet 0:478cfd88041f 2115 * \brief CSMA_CONFIG3 registers
group-Avnet 0:478cfd88041f 2116 * \code
group-Avnet 0:478cfd88041f 2117 * Default value: 0xFF
group-Avnet 0:478cfd88041f 2118 * Read Write
group-Avnet 0:478cfd88041f 2119 * 7:0 BU_COUNTER_SEED_MSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB)
group-Avnet 0:478cfd88041f 2120 * \endcode
group-Avnet 0:478cfd88041f 2121 */
group-Avnet 0:478cfd88041f 2122 #define CSMA_CONFIG3_BASE ((uint8_t)0x64) /*!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB) */
group-Avnet 0:478cfd88041f 2123
group-Avnet 0:478cfd88041f 2124 /**
group-Avnet 0:478cfd88041f 2125 * @}
group-Avnet 0:478cfd88041f 2126 */
group-Avnet 0:478cfd88041f 2127
group-Avnet 0:478cfd88041f 2128 /** @defgroup CSMA_CONFIG2_Register
group-Avnet 0:478cfd88041f 2129 * @{
group-Avnet 0:478cfd88041f 2130 */
group-Avnet 0:478cfd88041f 2131
group-Avnet 0:478cfd88041f 2132 /**
group-Avnet 0:478cfd88041f 2133 * \brief CSMA_CONFIG2 registers
group-Avnet 0:478cfd88041f 2134 * \code
group-Avnet 0:478cfd88041f 2135 * Default value: 0x00
group-Avnet 0:478cfd88041f 2136 * Read Write
group-Avnet 0:478cfd88041f 2137 * 7:0 BU_COUNTER_SEED_LSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB)
group-Avnet 0:478cfd88041f 2138 * \endcode
group-Avnet 0:478cfd88041f 2139 */
group-Avnet 0:478cfd88041f 2140 #define CSMA_CONFIG2_BASE ((uint8_t)0x65) /*!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB) */
group-Avnet 0:478cfd88041f 2141
group-Avnet 0:478cfd88041f 2142 /**
group-Avnet 0:478cfd88041f 2143 * @}
group-Avnet 0:478cfd88041f 2144 */
group-Avnet 0:478cfd88041f 2145
group-Avnet 0:478cfd88041f 2146 /** @defgroup CSMA_CONFIG1_Register
group-Avnet 0:478cfd88041f 2147 * @{
group-Avnet 0:478cfd88041f 2148 */
group-Avnet 0:478cfd88041f 2149
group-Avnet 0:478cfd88041f 2150 /**
group-Avnet 0:478cfd88041f 2151 * \brief CSMA_CONFIG1 registers
group-Avnet 0:478cfd88041f 2152 * \code
group-Avnet 0:478cfd88041f 2153 * Default value: 0x04
group-Avnet 0:478cfd88041f 2154 * Read Write
group-Avnet 0:478cfd88041f 2155 * 7:2 BU_PRESCALER[5:0]: Used to program the back-off unit BU
group-Avnet 0:478cfd88041f 2156 *
group-Avnet 0:478cfd88041f 2157 * 1:0 CCA_PERIOD[1:0]: Used to program the Tcca time (64 / 128 /256 / 512 × Tbit.
group-Avnet 0:478cfd88041f 2158 * \endcode
group-Avnet 0:478cfd88041f 2159 */
group-Avnet 0:478cfd88041f 2160 #define CSMA_CONFIG1_BASE ((uint8_t)0x66) /*!< CSMA/CA: Prescaler of the back-off time unit (BU); CCA period */
group-Avnet 0:478cfd88041f 2161
group-Avnet 0:478cfd88041f 2162 #define CSMA_CCA_PERIOD_64TBIT ((uint8_t)0x00) /*!< CSMA/CA: Sets CCA period to 64*TBIT */
group-Avnet 0:478cfd88041f 2163 #define CSMA_CCA_PERIOD_128TBIT ((uint8_t)0x01) /*!< CSMA/CA: Sets CCA period to 128*TBIT */
group-Avnet 0:478cfd88041f 2164 #define CSMA_CCA_PERIOD_256TBIT ((uint8_t)0x02) /*!< CSMA/CA: Sets CCA period to 256*TBIT */
group-Avnet 0:478cfd88041f 2165 #define CSMA_CCA_PERIOD_512TBIT ((uint8_t)0x03) /*!< CSMA/CA: Sets CCA period to 512*TBIT */
group-Avnet 0:478cfd88041f 2166
group-Avnet 0:478cfd88041f 2167 /**
group-Avnet 0:478cfd88041f 2168 * @}
group-Avnet 0:478cfd88041f 2169 */
group-Avnet 0:478cfd88041f 2170
group-Avnet 0:478cfd88041f 2171 /** @defgroup CSMA_CONFIG0_Register
group-Avnet 0:478cfd88041f 2172 * @{
group-Avnet 0:478cfd88041f 2173 */
group-Avnet 0:478cfd88041f 2174
group-Avnet 0:478cfd88041f 2175 /**
group-Avnet 0:478cfd88041f 2176 * \brief CSMA_CONFIG0 registers
group-Avnet 0:478cfd88041f 2177 * \code
group-Avnet 0:478cfd88041f 2178 * Default value: 0x00
group-Avnet 0:478cfd88041f 2179 * Read Write
group-Avnet 0:478cfd88041f 2180 * 7:4 CCA_LENGTH[3:0]: Used to program the Tlisten time
group-Avnet 0:478cfd88041f 2181 *
group-Avnet 0:478cfd88041f 2182 * 3 Reserved.
group-Avnet 0:478cfd88041f 2183 *
group-Avnet 0:478cfd88041f 2184 * 2:0 NBACKOFF_MAX[2:0]: Max number of back-off cycles.
group-Avnet 0:478cfd88041f 2185 * \endcode
group-Avnet 0:478cfd88041f 2186 */
group-Avnet 0:478cfd88041f 2187 #define CSMA_CONFIG0_BASE ((uint8_t)0x67) /*!< CSMA/CA: CCA lenght; Max number of backoff cycles */
group-Avnet 0:478cfd88041f 2188
group-Avnet 0:478cfd88041f 2189 /**
group-Avnet 0:478cfd88041f 2190 * @}
group-Avnet 0:478cfd88041f 2191 */
group-Avnet 0:478cfd88041f 2192
group-Avnet 0:478cfd88041f 2193 /**
group-Avnet 0:478cfd88041f 2194 * @}
group-Avnet 0:478cfd88041f 2195 */
group-Avnet 0:478cfd88041f 2196
group-Avnet 0:478cfd88041f 2197
group-Avnet 0:478cfd88041f 2198 /** @defgroup Link_Quality_Registers
group-Avnet 0:478cfd88041f 2199 * @{
group-Avnet 0:478cfd88041f 2200 */
group-Avnet 0:478cfd88041f 2201
group-Avnet 0:478cfd88041f 2202 /** @defgroup QI_Register
group-Avnet 0:478cfd88041f 2203 * @{
group-Avnet 0:478cfd88041f 2204 */
group-Avnet 0:478cfd88041f 2205
group-Avnet 0:478cfd88041f 2206 /**
group-Avnet 0:478cfd88041f 2207 * \brief QI register
group-Avnet 0:478cfd88041f 2208 * \code
group-Avnet 0:478cfd88041f 2209 * Read Write
group-Avnet 0:478cfd88041f 2210 * Default value: 0x02
group-Avnet 0:478cfd88041f 2211 *
group-Avnet 0:478cfd88041f 2212 * 7:6 SQI_TH[1:0]: SQI threshold according to the formula: 8*SYNC_LEN - 2*SQI_TH
group-Avnet 0:478cfd88041f 2213 *
group-Avnet 0:478cfd88041f 2214 * 5:2 PQI_TH[3:0]: PQI threshold according to the formula: 4*PQI_THR
group-Avnet 0:478cfd88041f 2215 *
group-Avnet 0:478cfd88041f 2216 *
group-Avnet 0:478cfd88041f 2217 * 1 SQI_EN[0]: SQI enable
group-Avnet 0:478cfd88041f 2218 * 1 - Enable
group-Avnet 0:478cfd88041f 2219 * 0 - Disable
group-Avnet 0:478cfd88041f 2220 *
group-Avnet 0:478cfd88041f 2221 * 0 PQI_EN[0]: PQI enable
group-Avnet 0:478cfd88041f 2222 * 1 - Enable
group-Avnet 0:478cfd88041f 2223 * 0 - Disable
group-Avnet 0:478cfd88041f 2224 * \endcode
group-Avnet 0:478cfd88041f 2225 */
group-Avnet 0:478cfd88041f 2226 #define QI_BASE ((uint8_t)0x3A) /*!< QI register */
group-Avnet 0:478cfd88041f 2227
group-Avnet 0:478cfd88041f 2228 #define QI_PQI_MASK ((uint8_t)0x01) /*!< PQI enable/disable */
group-Avnet 0:478cfd88041f 2229 #define QI_SQI_MASK ((uint8_t)0x02) /*!< SQI enable/disable */
group-Avnet 0:478cfd88041f 2230
group-Avnet 0:478cfd88041f 2231 /**
group-Avnet 0:478cfd88041f 2232 * @}
group-Avnet 0:478cfd88041f 2233 */
group-Avnet 0:478cfd88041f 2234
group-Avnet 0:478cfd88041f 2235 /** @defgroup LINK_QUALIF2
group-Avnet 0:478cfd88041f 2236 * @{
group-Avnet 0:478cfd88041f 2237 */
group-Avnet 0:478cfd88041f 2238
group-Avnet 0:478cfd88041f 2239 /**
group-Avnet 0:478cfd88041f 2240 * \brief LINK_QUALIF2 registers
group-Avnet 0:478cfd88041f 2241 * \code
group-Avnet 0:478cfd88041f 2242 * Default value: 0x00
group-Avnet 0:478cfd88041f 2243 * Read
group-Avnet 0:478cfd88041f 2244 *
group-Avnet 0:478cfd88041f 2245 * 7:0 PQI[7:0]: PQI value of the received packet
group-Avnet 0:478cfd88041f 2246 * \endcode
group-Avnet 0:478cfd88041f 2247 */
group-Avnet 0:478cfd88041f 2248 #define LINK_QUALIF2_BASE ((uint8_t)(0xC5)) /*!< PQI value of the received packet */
group-Avnet 0:478cfd88041f 2249
group-Avnet 0:478cfd88041f 2250 /**
group-Avnet 0:478cfd88041f 2251 * @}
group-Avnet 0:478cfd88041f 2252 */
group-Avnet 0:478cfd88041f 2253
group-Avnet 0:478cfd88041f 2254 /** @defgroup LINK_QUALIF1
group-Avnet 0:478cfd88041f 2255 * @{
group-Avnet 0:478cfd88041f 2256 */
group-Avnet 0:478cfd88041f 2257
group-Avnet 0:478cfd88041f 2258 /**
group-Avnet 0:478cfd88041f 2259 * \brief LINK_QUALIF1 registers
group-Avnet 0:478cfd88041f 2260 * \code
group-Avnet 0:478cfd88041f 2261 * Default value: 0x00
group-Avnet 0:478cfd88041f 2262 * Read
group-Avnet 0:478cfd88041f 2263 *
group-Avnet 0:478cfd88041f 2264 * 7 CS: Carrier Sense indication
group-Avnet 0:478cfd88041f 2265 *
group-Avnet 0:478cfd88041f 2266 * 6:0 SQI[6:0]: SQI value of the received packet
group-Avnet 0:478cfd88041f 2267 * \endcode
group-Avnet 0:478cfd88041f 2268 */
group-Avnet 0:478cfd88041f 2269 #define LINK_QUALIF1_BASE ((uint8_t)(0xC6)) /*!< Carrier sense indication [7]; SQI value of the received packet */
group-Avnet 0:478cfd88041f 2270
group-Avnet 0:478cfd88041f 2271 #define LINK_QUALIF1_CS ((uint8_t)(0x80)) /*!< Carrier sense indication [7] */
group-Avnet 0:478cfd88041f 2272
group-Avnet 0:478cfd88041f 2273 /**
group-Avnet 0:478cfd88041f 2274 * @}
group-Avnet 0:478cfd88041f 2275 */
group-Avnet 0:478cfd88041f 2276
group-Avnet 0:478cfd88041f 2277 /** @defgroup LINK_QUALIF0
group-Avnet 0:478cfd88041f 2278 * @{
group-Avnet 0:478cfd88041f 2279 */
group-Avnet 0:478cfd88041f 2280
group-Avnet 0:478cfd88041f 2281 /**
group-Avnet 0:478cfd88041f 2282 * \brief LINK_QUALIF0 registers
group-Avnet 0:478cfd88041f 2283 * \code
group-Avnet 0:478cfd88041f 2284 * Default value: 0x00
group-Avnet 0:478cfd88041f 2285 * Read
group-Avnet 0:478cfd88041f 2286 *
group-Avnet 0:478cfd88041f 2287 * 7:4 LQI [3:0]: LQI value of the received packet
group-Avnet 0:478cfd88041f 2288 *
group-Avnet 0:478cfd88041f 2289 * 3:0 AGC_WORD[3:0]: AGC word of the received packet
group-Avnet 0:478cfd88041f 2290 * \endcode
group-Avnet 0:478cfd88041f 2291 */
group-Avnet 0:478cfd88041f 2292 #define LINK_QUALIF0_BASE ((uint8_t)(0xC7)) /*!< LQI value of the received packet [7:4]; AGC word of the received packet [3:0] */
group-Avnet 0:478cfd88041f 2293
group-Avnet 0:478cfd88041f 2294 /**
group-Avnet 0:478cfd88041f 2295 * @}
group-Avnet 0:478cfd88041f 2296 */
group-Avnet 0:478cfd88041f 2297
group-Avnet 0:478cfd88041f 2298 /** @defgroup RSSI_LEVEL
group-Avnet 0:478cfd88041f 2299 * @{
group-Avnet 0:478cfd88041f 2300 */
group-Avnet 0:478cfd88041f 2301
group-Avnet 0:478cfd88041f 2302 /**
group-Avnet 0:478cfd88041f 2303 * \brief RSSI_LEVEL registers
group-Avnet 0:478cfd88041f 2304 * \code
group-Avnet 0:478cfd88041f 2305 * Default value: 0x00
group-Avnet 0:478cfd88041f 2306 * Read
group-Avnet 0:478cfd88041f 2307 *
group-Avnet 0:478cfd88041f 2308 * 7:0 RSSI_LEVEL[7:0]: RSSI level of the received packet
group-Avnet 0:478cfd88041f 2309 * \endcode
group-Avnet 0:478cfd88041f 2310 */
group-Avnet 0:478cfd88041f 2311 #define RSSI_LEVEL_BASE ((uint8_t)(0xC8)) /*!< RSSI level of the received packet */
group-Avnet 0:478cfd88041f 2312
group-Avnet 0:478cfd88041f 2313 /**
group-Avnet 0:478cfd88041f 2314 * @}
group-Avnet 0:478cfd88041f 2315 */
group-Avnet 0:478cfd88041f 2316
group-Avnet 0:478cfd88041f 2317 /** @defgroup RSSI_FLT_Register
group-Avnet 0:478cfd88041f 2318 * @{
group-Avnet 0:478cfd88041f 2319 */
group-Avnet 0:478cfd88041f 2320
group-Avnet 0:478cfd88041f 2321 /**
group-Avnet 0:478cfd88041f 2322 * \brief RSSI register
group-Avnet 0:478cfd88041f 2323 * \code
group-Avnet 0:478cfd88041f 2324 * Read Write
group-Avnet 0:478cfd88041f 2325 * Default value: 0xF3
group-Avnet 0:478cfd88041f 2326 * 7:4 RSSI_FLT[3:0]: Gain of the RSSI filter
group-Avnet 0:478cfd88041f 2327 *
group-Avnet 0:478cfd88041f 2328 * 3:2 CS_MODE[1:0]: AFC loop gain in slow mode (2's log)
group-Avnet 0:478cfd88041f 2329 *
group-Avnet 0:478cfd88041f 2330 * CS_MODE1 | CS_MODE0 | CS Mode
group-Avnet 0:478cfd88041f 2331 * -----------------------------------------------------------------------------------------
group-Avnet 0:478cfd88041f 2332 * 0 | 0 | Static CS
group-Avnet 0:478cfd88041f 2333 * 0 | 1 | Dynamic CS with 6dB dynamic threshold
group-Avnet 0:478cfd88041f 2334 * 1 | 0 | Dynamic CS with 12dB dynamic threshold
group-Avnet 0:478cfd88041f 2335 * 1 | 1 | Dynamic CS with 18dB dynamic threshold
group-Avnet 0:478cfd88041f 2336 *
group-Avnet 0:478cfd88041f 2337 * 1:0 OOK_PEAK_DECAY[1:0]: Peak decay control for OOK: 3 slow decay; 0 fast decay
group-Avnet 0:478cfd88041f 2338 *
group-Avnet 0:478cfd88041f 2339 * \endcode
group-Avnet 0:478cfd88041f 2340 */
group-Avnet 0:478cfd88041f 2341 #define RSSI_FLT_BASE ((uint8_t)0x21) /*!< Gain of the RSSI filter; lower value is fast but inaccurate,
group-Avnet 0:478cfd88041f 2342 higher value is slow and more accurate */
group-Avnet 0:478cfd88041f 2343 #define RSSI_FLT_CS_MODE_MASK ((uint8_t)0x0C) /*!< Carrier sense mode mask */
group-Avnet 0:478cfd88041f 2344 #define RSSI_FLT_CS_MODE_STATIC ((uint8_t)0x00) /*!< Carrier sense mode; static carrier sensing */
group-Avnet 0:478cfd88041f 2345 #define RSSI_FLT_CS_MODE_DYNAMIC_6 ((uint8_t)0x04) /*!< Carrier sense mode; dynamic carrier sensing with 6dB threshold */
group-Avnet 0:478cfd88041f 2346 #define RSSI_FLT_CS_MODE_DYNAMIC_12 ((uint8_t)0x08) /*!< Carrier sense mode; dynamic carrier sensing with 12dB threshold */
group-Avnet 0:478cfd88041f 2347 #define RSSI_FLT_CS_MODE_DYNAMIC_18 ((uint8_t)0x0C) /*!< Carrier sense mode; dynamic carrier sensing with 18dB threshold */
group-Avnet 0:478cfd88041f 2348 #define RSSI_FLT_OOK_PEAK_DECAY_MASK ((uint8_t)0x03) /*!< Peak decay control for OOK mask */
group-Avnet 0:478cfd88041f 2349 #define RSSI_FLT_OOK_PEAK_DECAY_FAST ((uint8_t)0x00) /*!< Peak decay control for OOK: fast decay */
group-Avnet 0:478cfd88041f 2350 #define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_FAST ((uint8_t)0x01) /*!< Peak decay control for OOK: medium_fast decay */
group-Avnet 0:478cfd88041f 2351 #define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_SLOW ((uint8_t)0x02) /*!< Peak decay control for OOK: medium_fast decay */
group-Avnet 0:478cfd88041f 2352 #define RSSI_FLT_OOK_PEAK_DECAY_SLOW ((uint8_t)0x03) /*!< Peak decay control for OOK: slow decay */
group-Avnet 0:478cfd88041f 2353
group-Avnet 0:478cfd88041f 2354 /**
group-Avnet 0:478cfd88041f 2355 * @}
group-Avnet 0:478cfd88041f 2356 */
group-Avnet 0:478cfd88041f 2357
group-Avnet 0:478cfd88041f 2358 /** @defgroup RSSI_TH_Register
group-Avnet 0:478cfd88041f 2359 * @{
group-Avnet 0:478cfd88041f 2360 */
group-Avnet 0:478cfd88041f 2361
group-Avnet 0:478cfd88041f 2362 /**
group-Avnet 0:478cfd88041f 2363 * \brief RSSI_TH register
group-Avnet 0:478cfd88041f 2364 * \code
group-Avnet 0:478cfd88041f 2365 * Read Write
group-Avnet 0:478cfd88041f 2366 * Default value: 0x24
group-Avnet 0:478cfd88041f 2367 *
group-Avnet 0:478cfd88041f 2368 * 7:0 RSSI_THRESHOLD [7:0]: Signal detect threshold in 0.5dB. -120dBm corresponds to 20
group-Avnet 0:478cfd88041f 2369 * \endcode
group-Avnet 0:478cfd88041f 2370 */
group-Avnet 0:478cfd88041f 2371 #define RSSI_TH_BASE ((uint8_t)0x22) /*!< Signal detect threshold in 0.5dB stp. 20 correspond to -120 dBm */
group-Avnet 0:478cfd88041f 2372
group-Avnet 0:478cfd88041f 2373 /**
group-Avnet 0:478cfd88041f 2374 * @}
group-Avnet 0:478cfd88041f 2375 */
group-Avnet 0:478cfd88041f 2376
group-Avnet 0:478cfd88041f 2377 /**
group-Avnet 0:478cfd88041f 2378 * @}
group-Avnet 0:478cfd88041f 2379 */
group-Avnet 0:478cfd88041f 2380
group-Avnet 0:478cfd88041f 2381
group-Avnet 0:478cfd88041f 2382 /** @defgroup FIFO_Registers
group-Avnet 0:478cfd88041f 2383 * @{
group-Avnet 0:478cfd88041f 2384 */
group-Avnet 0:478cfd88041f 2385
group-Avnet 0:478cfd88041f 2386 /** @defgroup FIFO_CONFIG3_Register
group-Avnet 0:478cfd88041f 2387 * @{
group-Avnet 0:478cfd88041f 2388 */
group-Avnet 0:478cfd88041f 2389
group-Avnet 0:478cfd88041f 2390 /**
group-Avnet 0:478cfd88041f 2391 * \brief FIFO_CONFIG3 registers
group-Avnet 0:478cfd88041f 2392 * \code
group-Avnet 0:478cfd88041f 2393 * Default value: 0x30
group-Avnet 0:478cfd88041f 2394 * Read Write
group-Avnet 0:478cfd88041f 2395 * 7 Reserved.
group-Avnet 0:478cfd88041f 2396 *
group-Avnet 0:478cfd88041f 2397 * 6:0 rxafthr [6:0]: FIFO Almost Full threshold for rx fifo.
group-Avnet 0:478cfd88041f 2398 *
group-Avnet 0:478cfd88041f 2399 * \endcode
group-Avnet 0:478cfd88041f 2400 */
group-Avnet 0:478cfd88041f 2401 #define FIFO_CONFIG3_RXAFTHR_BASE ((uint8_t)0x3E) /*!< FIFO Almost Full threshold for rx fifo [6:0] */
group-Avnet 0:478cfd88041f 2402
group-Avnet 0:478cfd88041f 2403 /**
group-Avnet 0:478cfd88041f 2404 * @}
group-Avnet 0:478cfd88041f 2405 */
group-Avnet 0:478cfd88041f 2406
group-Avnet 0:478cfd88041f 2407 /** @defgroup FIFO_CONFIG2_Register
group-Avnet 0:478cfd88041f 2408 * @{
group-Avnet 0:478cfd88041f 2409 */
group-Avnet 0:478cfd88041f 2410
group-Avnet 0:478cfd88041f 2411 /**
group-Avnet 0:478cfd88041f 2412 * \brief FIFO_CONFIG2 registers
group-Avnet 0:478cfd88041f 2413 * \code
group-Avnet 0:478cfd88041f 2414 * Default value: 0x30
group-Avnet 0:478cfd88041f 2415 * Read Write
group-Avnet 0:478cfd88041f 2416 * 7 Reserved.
group-Avnet 0:478cfd88041f 2417 *
group-Avnet 0:478cfd88041f 2418 * 6:0 rxaethr [6:0]: FIFO Almost Empty threshold for rx fifo.
group-Avnet 0:478cfd88041f 2419 *
group-Avnet 0:478cfd88041f 2420 * \endcode
group-Avnet 0:478cfd88041f 2421 */
group-Avnet 0:478cfd88041f 2422 #define FIFO_CONFIG2_RXAETHR_BASE ((uint8_t)0x3F) /*!< FIFO Almost Empty threshold for rx fifo [6:0] */
group-Avnet 0:478cfd88041f 2423
group-Avnet 0:478cfd88041f 2424 /**
group-Avnet 0:478cfd88041f 2425 * @}
group-Avnet 0:478cfd88041f 2426 */
group-Avnet 0:478cfd88041f 2427
group-Avnet 0:478cfd88041f 2428 /** @defgroup FIFO_CONFIG1_Register
group-Avnet 0:478cfd88041f 2429 * @{
group-Avnet 0:478cfd88041f 2430 */
group-Avnet 0:478cfd88041f 2431
group-Avnet 0:478cfd88041f 2432 /**
group-Avnet 0:478cfd88041f 2433 * \brief FIFO_CONFIG1 registers
group-Avnet 0:478cfd88041f 2434 * \code
group-Avnet 0:478cfd88041f 2435 * Default value: 0x30
group-Avnet 0:478cfd88041f 2436 * Read Write
group-Avnet 0:478cfd88041f 2437 * 7 Reserved.
group-Avnet 0:478cfd88041f 2438 *
group-Avnet 0:478cfd88041f 2439 * 6:0 txafthr [6:0]: FIFO Almost Full threshold for tx fifo.
group-Avnet 0:478cfd88041f 2440 *
group-Avnet 0:478cfd88041f 2441 * \endcode
group-Avnet 0:478cfd88041f 2442 */
group-Avnet 0:478cfd88041f 2443 #define FIFO_CONFIG1_TXAFTHR_BASE ((uint8_t)0x40) /*!< FIFO Almost Full threshold for tx fifo [6:0] */
group-Avnet 0:478cfd88041f 2444
group-Avnet 0:478cfd88041f 2445 /**
group-Avnet 0:478cfd88041f 2446 * @}
group-Avnet 0:478cfd88041f 2447 */
group-Avnet 0:478cfd88041f 2448
group-Avnet 0:478cfd88041f 2449 /** @defgroup FIFO_CONFIG0_Register
group-Avnet 0:478cfd88041f 2450 * @{
group-Avnet 0:478cfd88041f 2451 */
group-Avnet 0:478cfd88041f 2452
group-Avnet 0:478cfd88041f 2453 /**
group-Avnet 0:478cfd88041f 2454 * \brief FIFO_CONFIG0 registers
group-Avnet 0:478cfd88041f 2455 * \code
group-Avnet 0:478cfd88041f 2456 * Default value: 0x30
group-Avnet 0:478cfd88041f 2457 * Read Write
group-Avnet 0:478cfd88041f 2458 * 7 Reserved.
group-Avnet 0:478cfd88041f 2459 *
group-Avnet 0:478cfd88041f 2460 * 6:0 txaethr [6:0]: FIFO Almost Empty threshold for tx fifo.
group-Avnet 0:478cfd88041f 2461 *
group-Avnet 0:478cfd88041f 2462 * \endcode
group-Avnet 0:478cfd88041f 2463 */
group-Avnet 0:478cfd88041f 2464 #define FIFO_CONFIG0_TXAETHR_BASE ((uint8_t)0x41) /*!< FIFO Almost Empty threshold for tx fifo [6:0] */
group-Avnet 0:478cfd88041f 2465
group-Avnet 0:478cfd88041f 2466 /**
group-Avnet 0:478cfd88041f 2467 * @}
group-Avnet 0:478cfd88041f 2468 */
group-Avnet 0:478cfd88041f 2469
group-Avnet 0:478cfd88041f 2470 /** @defgroup LINEAR_FIFO_STATUS1_Register
group-Avnet 0:478cfd88041f 2471 * @{
group-Avnet 0:478cfd88041f 2472 */
group-Avnet 0:478cfd88041f 2473
group-Avnet 0:478cfd88041f 2474 /**
group-Avnet 0:478cfd88041f 2475 * \brief LINEAR_FIFO_STATUS1 registers
group-Avnet 0:478cfd88041f 2476 * \code
group-Avnet 0:478cfd88041f 2477 * Default value: 0x00
group-Avnet 0:478cfd88041f 2478 * Read
group-Avnet 0:478cfd88041f 2479 *
group-Avnet 0:478cfd88041f 2480 * 7 Reserved.
group-Avnet 0:478cfd88041f 2481 *
group-Avnet 0:478cfd88041f 2482 * 6:0 elem_txfifo[6:0]: Number of elements in the linear TXFIFO (<=96)
group-Avnet 0:478cfd88041f 2483 * \endcode
group-Avnet 0:478cfd88041f 2484 */
group-Avnet 0:478cfd88041f 2485 #define LINEAR_FIFO_STATUS1_BASE ((uint8_t)(0xE6)) /*!< Number of elements in the linear TX FIFO [6:0] (<=96) */
group-Avnet 0:478cfd88041f 2486
group-Avnet 0:478cfd88041f 2487 /**
group-Avnet 0:478cfd88041f 2488 * @}
group-Avnet 0:478cfd88041f 2489 */
group-Avnet 0:478cfd88041f 2490
group-Avnet 0:478cfd88041f 2491 /** @defgroup LINEAR_FIFO_STATUS0_Register
group-Avnet 0:478cfd88041f 2492 * @{
group-Avnet 0:478cfd88041f 2493 */
group-Avnet 0:478cfd88041f 2494
group-Avnet 0:478cfd88041f 2495 /**
group-Avnet 0:478cfd88041f 2496 * \brief LINEAR_FIFO_STATUS0 registers
group-Avnet 0:478cfd88041f 2497 * \code
group-Avnet 0:478cfd88041f 2498 * Default value: 0x00
group-Avnet 0:478cfd88041f 2499 * Read
group-Avnet 0:478cfd88041f 2500 *
group-Avnet 0:478cfd88041f 2501 * 7 Reserved.
group-Avnet 0:478cfd88041f 2502 *
group-Avnet 0:478cfd88041f 2503 * 6:0 elem_rxfifo[6:0]: Number of elements in the linear RXFIFO (<=96)
group-Avnet 0:478cfd88041f 2504 * \endcode
group-Avnet 0:478cfd88041f 2505 */
group-Avnet 0:478cfd88041f 2506 #define LINEAR_FIFO_STATUS0_BASE ((uint8_t)(0xE7)) /*!< Number of elements in the linear RX FIFO [6:0] (<=96) */
group-Avnet 0:478cfd88041f 2507
group-Avnet 0:478cfd88041f 2508 /**
group-Avnet 0:478cfd88041f 2509 * @}
group-Avnet 0:478cfd88041f 2510 */
group-Avnet 0:478cfd88041f 2511
group-Avnet 0:478cfd88041f 2512
group-Avnet 0:478cfd88041f 2513 /**
group-Avnet 0:478cfd88041f 2514 * @}
group-Avnet 0:478cfd88041f 2515 */
group-Avnet 0:478cfd88041f 2516
group-Avnet 0:478cfd88041f 2517
group-Avnet 0:478cfd88041f 2518 /** @defgroup Calibration_Registers
group-Avnet 0:478cfd88041f 2519 * @{
group-Avnet 0:478cfd88041f 2520 */
group-Avnet 0:478cfd88041f 2521
group-Avnet 0:478cfd88041f 2522 /** @defgroup RCO_VCO_CALIBR_IN2_Register
group-Avnet 0:478cfd88041f 2523 * @{
group-Avnet 0:478cfd88041f 2524 */
group-Avnet 0:478cfd88041f 2525
group-Avnet 0:478cfd88041f 2526 /**
group-Avnet 0:478cfd88041f 2527 * \brief RCO_VCO_CALIBR_IN2 registers
group-Avnet 0:478cfd88041f 2528 * \code
group-Avnet 0:478cfd88041f 2529 * Default value: 0x70
group-Avnet 0:478cfd88041f 2530 * Read Write
group-Avnet 0:478cfd88041f 2531 * 7:4 RWT_IN[3:0]: RaWThermometric word value for the RCO [7:4]
group-Avnet 0:478cfd88041f 2532 *
group-Avnet 0:478cfd88041f 2533 * 3:0 RFB_IN[4:1]: ResistorFineBit word value for the RCO (first 4 bits)
group-Avnet 0:478cfd88041f 2534 * \endcode
group-Avnet 0:478cfd88041f 2535 */
group-Avnet 0:478cfd88041f 2536 #define RCO_VCO_CALIBR_IN2_BASE ((uint8_t)0x6D) /*!< RaWThermometric word value for the RCO [7:4]; ResistorFineBit word value for the RCO [3:0] */
group-Avnet 0:478cfd88041f 2537
group-Avnet 0:478cfd88041f 2538 /**
group-Avnet 0:478cfd88041f 2539 * @}
group-Avnet 0:478cfd88041f 2540 */
group-Avnet 0:478cfd88041f 2541
group-Avnet 0:478cfd88041f 2542 /** @defgroup RCO_VCO_CALIBR_IN1_Register
group-Avnet 0:478cfd88041f 2543 * @{
group-Avnet 0:478cfd88041f 2544 */
group-Avnet 0:478cfd88041f 2545
group-Avnet 0:478cfd88041f 2546 /**
group-Avnet 0:478cfd88041f 2547 * \brief RCO_VCO_CALIBR_IN1 registers
group-Avnet 0:478cfd88041f 2548 * \code
group-Avnet 0:478cfd88041f 2549 * Default value: 0x48
group-Avnet 0:478cfd88041f 2550 * Read Write
group-Avnet 0:478cfd88041f 2551 *
group-Avnet 0:478cfd88041f 2552 * 7 RFB_IN[0]: ResistorFineBit word value for the RCO (LSb)
group-Avnet 0:478cfd88041f 2553 *
group-Avnet 0:478cfd88041f 2554 * 6:0 VCO_CALIBR_TX[6:0]: Word value for the VCO to be used in TX mode
group-Avnet 0:478cfd88041f 2555 * \endcode
group-Avnet 0:478cfd88041f 2556 */
group-Avnet 0:478cfd88041f 2557 #define RCO_VCO_CALIBR_IN1_BASE ((uint8_t)0x6E) /*!< ResistorFineBit word value for the RCO [7]; Word value for the VCO to be used in TX mode [6:0]*/
group-Avnet 0:478cfd88041f 2558
group-Avnet 0:478cfd88041f 2559 /**
group-Avnet 0:478cfd88041f 2560 * @}
group-Avnet 0:478cfd88041f 2561 */
group-Avnet 0:478cfd88041f 2562
group-Avnet 0:478cfd88041f 2563 /** @defgroup RCO_VCO_CALIBR_IN0_Register
group-Avnet 0:478cfd88041f 2564 * @{
group-Avnet 0:478cfd88041f 2565 */
group-Avnet 0:478cfd88041f 2566
group-Avnet 0:478cfd88041f 2567 /**
group-Avnet 0:478cfd88041f 2568 * \brief RCO_VCO_CALIBR_IN0 registers
group-Avnet 0:478cfd88041f 2569 * \code
group-Avnet 0:478cfd88041f 2570 * Default value: 0x48
group-Avnet 0:478cfd88041f 2571 * Read Write
group-Avnet 0:478cfd88041f 2572 *
group-Avnet 0:478cfd88041f 2573 * 7 Reserved.
group-Avnet 0:478cfd88041f 2574 *
group-Avnet 0:478cfd88041f 2575 * 6:0 VCO_CALIBR_RX[6:0]: Word value for the VCO to be used in RX mode
group-Avnet 0:478cfd88041f 2576 * \endcode
group-Avnet 0:478cfd88041f 2577 */
group-Avnet 0:478cfd88041f 2578 #define RCO_VCO_CALIBR_IN0_BASE ((uint8_t)0x6F) /*!< Word value for the VCO to be used in RX mode [6:0] */
group-Avnet 0:478cfd88041f 2579
group-Avnet 0:478cfd88041f 2580 /**
group-Avnet 0:478cfd88041f 2581 * @}
group-Avnet 0:478cfd88041f 2582 */
group-Avnet 0:478cfd88041f 2583
group-Avnet 0:478cfd88041f 2584 /** @defgroup RCO_VCO_CALIBR_OUT1_Register
group-Avnet 0:478cfd88041f 2585 * @{
group-Avnet 0:478cfd88041f 2586 */
group-Avnet 0:478cfd88041f 2587
group-Avnet 0:478cfd88041f 2588 /**
group-Avnet 0:478cfd88041f 2589 * \brief RCO_VCO_CALIBR_OUT1 registers
group-Avnet 0:478cfd88041f 2590 * \code
group-Avnet 0:478cfd88041f 2591 * Default value: 0x00
group-Avnet 0:478cfd88041f 2592 * Read
group-Avnet 0:478cfd88041f 2593 *
group-Avnet 0:478cfd88041f 2594 * 7:4 RWT_OUT[3:0]: RWT word from internal RCO calibrator
group-Avnet 0:478cfd88041f 2595 *
group-Avnet 0:478cfd88041f 2596 * 3:0 RFB_OUT[4:1]: RFB word from internal RCO calibrator (upper part)
group-Avnet 0:478cfd88041f 2597 * \endcode
group-Avnet 0:478cfd88041f 2598 */
group-Avnet 0:478cfd88041f 2599 #define RCO_VCO_CALIBR_OUT1_BASE ((uint8_t)(0xE4)) /*!< RaWThermometric RWT word from internal RCO calibrator [7];
group-Avnet 0:478cfd88041f 2600 ResistorFineBit RFB word from internal RCO oscillator [6:0] */
group-Avnet 0:478cfd88041f 2601 /**
group-Avnet 0:478cfd88041f 2602 * @}
group-Avnet 0:478cfd88041f 2603 */
group-Avnet 0:478cfd88041f 2604
group-Avnet 0:478cfd88041f 2605 /** @defgroup RCO_VCO_CALIBR_OUT0_Register
group-Avnet 0:478cfd88041f 2606 * @{
group-Avnet 0:478cfd88041f 2607 */
group-Avnet 0:478cfd88041f 2608
group-Avnet 0:478cfd88041f 2609 /**
group-Avnet 0:478cfd88041f 2610 * \brief RCO_VCO_CALIBR_OUT0 registers
group-Avnet 0:478cfd88041f 2611 * \code
group-Avnet 0:478cfd88041f 2612 * Default value: 0x00
group-Avnet 0:478cfd88041f 2613 * Read
group-Avnet 0:478cfd88041f 2614 *
group-Avnet 0:478cfd88041f 2615 * 7 RFB_OUT[0]: RFB word from internal RCO calibrator (last bit LSB)
group-Avnet 0:478cfd88041f 2616 *
group-Avnet 0:478cfd88041f 2617 * 6:0 VCO_CALIBR_DATA[6:0]: Output word from internal VCO calibrator
group-Avnet 0:478cfd88041f 2618 * \endcode
group-Avnet 0:478cfd88041f 2619 */
group-Avnet 0:478cfd88041f 2620 #define RCO_VCO_CALIBR_OUT0_BASE ((uint8_t)(0xE5)) /*!< ResistorFineBit RFB word from internal RCO oscillator [0];
group-Avnet 0:478cfd88041f 2621 Output word from internal calibrator [6:0]; */
group-Avnet 0:478cfd88041f 2622 /**
group-Avnet 0:478cfd88041f 2623 * @}
group-Avnet 0:478cfd88041f 2624 */
group-Avnet 0:478cfd88041f 2625
group-Avnet 0:478cfd88041f 2626 /**
group-Avnet 0:478cfd88041f 2627 * @}
group-Avnet 0:478cfd88041f 2628 */
group-Avnet 0:478cfd88041f 2629
group-Avnet 0:478cfd88041f 2630
group-Avnet 0:478cfd88041f 2631 /** @defgroup AES_Registers
group-Avnet 0:478cfd88041f 2632 * @{
group-Avnet 0:478cfd88041f 2633 */
group-Avnet 0:478cfd88041f 2634
group-Avnet 0:478cfd88041f 2635 /** @defgroup AES_KEY_IN_Register
group-Avnet 0:478cfd88041f 2636 * @{
group-Avnet 0:478cfd88041f 2637 */
group-Avnet 0:478cfd88041f 2638
group-Avnet 0:478cfd88041f 2639 /**
group-Avnet 0:478cfd88041f 2640 * \brief AES_KEY_INx registers
group-Avnet 0:478cfd88041f 2641 * \code
group-Avnet 0:478cfd88041f 2642 * Default value: 0x00
group-Avnet 0:478cfd88041f 2643 * Read Write
group-Avnet 0:478cfd88041f 2644 *
group-Avnet 0:478cfd88041f 2645 * 7:0 AES_KEY_INx[7:0]: AES engine key input (total - 128 bits)
group-Avnet 0:478cfd88041f 2646 * \endcode
group-Avnet 0:478cfd88041f 2647 */
group-Avnet 0:478cfd88041f 2648 #define AES_KEY_IN_15_BASE ((uint8_t)0x70) /*!< AES engine key input 15 */
group-Avnet 0:478cfd88041f 2649
group-Avnet 0:478cfd88041f 2650 #define AES_KEY_IN_14_BASE ((uint8_t)0x71) /*!< AES engine key input 14 */
group-Avnet 0:478cfd88041f 2651
group-Avnet 0:478cfd88041f 2652 #define AES_KEY_IN_13_BASE ((uint8_t)0x72) /*!< AES engine key input 13 */
group-Avnet 0:478cfd88041f 2653
group-Avnet 0:478cfd88041f 2654 #define AES_KEY_IN_12_BASE ((uint8_t)0x73) /*!< AES engine key input 12 */
group-Avnet 0:478cfd88041f 2655
group-Avnet 0:478cfd88041f 2656 #define AES_KEY_IN_11_BASE ((uint8_t)0x74) /*!< AES engine key input 11 */
group-Avnet 0:478cfd88041f 2657
group-Avnet 0:478cfd88041f 2658 #define AES_KEY_IN_10_BASE ((uint8_t)0x75) /*!< AES engine key input 10 */
group-Avnet 0:478cfd88041f 2659
group-Avnet 0:478cfd88041f 2660 #define AES_KEY_IN_9_BASE ((uint8_t)0x76) /*!< AES engine key input 9 */
group-Avnet 0:478cfd88041f 2661
group-Avnet 0:478cfd88041f 2662 #define AES_KEY_IN_8_BASE ((uint8_t)0x77) /*!< AES engine key input 8 */
group-Avnet 0:478cfd88041f 2663
group-Avnet 0:478cfd88041f 2664 #define AES_KEY_IN_7_BASE ((uint8_t)0x78) /*!< AES engine key input 7 */
group-Avnet 0:478cfd88041f 2665
group-Avnet 0:478cfd88041f 2666 #define AES_KEY_IN_6_BASE ((uint8_t)0x79) /*!< AES engine key input 6 */
group-Avnet 0:478cfd88041f 2667
group-Avnet 0:478cfd88041f 2668 #define AES_KEY_IN_5_BASE ((uint8_t)0x7A) /*!< AES engine key input 5 */
group-Avnet 0:478cfd88041f 2669
group-Avnet 0:478cfd88041f 2670 #define AES_KEY_IN_4_BASE ((uint8_t)0x7B) /*!< AES engine key input 4 */
group-Avnet 0:478cfd88041f 2671
group-Avnet 0:478cfd88041f 2672 #define AES_KEY_IN_3_BASE ((uint8_t)0x7C) /*!< AES engine key input 3 */
group-Avnet 0:478cfd88041f 2673
group-Avnet 0:478cfd88041f 2674 #define AES_KEY_IN_2_BASE ((uint8_t)0x7D) /*!< AES engine key input 2 */
group-Avnet 0:478cfd88041f 2675
group-Avnet 0:478cfd88041f 2676 #define AES_KEY_IN_1_BASE ((uint8_t)0x7E) /*!< AES engine key input 1 */
group-Avnet 0:478cfd88041f 2677
group-Avnet 0:478cfd88041f 2678 #define AES_KEY_IN_0_BASE ((uint8_t)0x7F) /*!< AES engine key input 0 */
group-Avnet 0:478cfd88041f 2679
group-Avnet 0:478cfd88041f 2680 /**
group-Avnet 0:478cfd88041f 2681 * @}
group-Avnet 0:478cfd88041f 2682 */
group-Avnet 0:478cfd88041f 2683
group-Avnet 0:478cfd88041f 2684 /** @defgroup AES_DATA_IN_Register
group-Avnet 0:478cfd88041f 2685 * @{
group-Avnet 0:478cfd88041f 2686 */
group-Avnet 0:478cfd88041f 2687
group-Avnet 0:478cfd88041f 2688 /**
group-Avnet 0:478cfd88041f 2689 * \brief AES_DATA_INx registers
group-Avnet 0:478cfd88041f 2690 * \code
group-Avnet 0:478cfd88041f 2691 * Default value: 0x00
group-Avnet 0:478cfd88041f 2692 * Read Write
group-Avnet 0:478cfd88041f 2693 *
group-Avnet 0:478cfd88041f 2694 * 7:0 AES_DATA_INx[7:0]: AES engine data input (total - 128 bits)
group-Avnet 0:478cfd88041f 2695 * \endcode
group-Avnet 0:478cfd88041f 2696 */
group-Avnet 0:478cfd88041f 2697 #define AES_DATA_IN_15_BASE ((uint8_t)0x80) /*!< AES engine data input 15
group-Avnet 0:478cfd88041f 2698 Take care: Address is in reverse order respect data numbering; eg.: 0x81 -> AES_data14[7:0] */
group-Avnet 0:478cfd88041f 2699 #define AES_DATA_IN_14_BASE ((uint8_t)0x81) /*!< AES engine data input 14 */
group-Avnet 0:478cfd88041f 2700
group-Avnet 0:478cfd88041f 2701 #define AES_DATA_IN_13_BASE ((uint8_t)0x82) /*!< AES engine data input 13 */
group-Avnet 0:478cfd88041f 2702
group-Avnet 0:478cfd88041f 2703 #define AES_DATA_IN_12_BASE ((uint8_t)0x83) /*!< AES engine data input 12 */
group-Avnet 0:478cfd88041f 2704
group-Avnet 0:478cfd88041f 2705 #define AES_DATA_IN_11_BASE ((uint8_t)0x84) /*!< AES engine data input 11 */
group-Avnet 0:478cfd88041f 2706
group-Avnet 0:478cfd88041f 2707 #define AES_DATA_IN_10_BASE ((uint8_t)0x85) /*!< AES engine data input 10 */
group-Avnet 0:478cfd88041f 2708
group-Avnet 0:478cfd88041f 2709 #define AES_DATA_IN_9_BASE ((uint8_t)0x86) /*!< AES engine data input 9 */
group-Avnet 0:478cfd88041f 2710
group-Avnet 0:478cfd88041f 2711 #define AES_DATA_IN_8_BASE ((uint8_t)0x87) /*!< AES engine data input 8 */
group-Avnet 0:478cfd88041f 2712
group-Avnet 0:478cfd88041f 2713 #define AES_DATA_IN_7_BASE ((uint8_t)0x88) /*!< AES engine data input 7 */
group-Avnet 0:478cfd88041f 2714
group-Avnet 0:478cfd88041f 2715 #define AES_DATA_IN_6_BASE ((uint8_t)0x89) /*!< AES engine data input 6 */
group-Avnet 0:478cfd88041f 2716
group-Avnet 0:478cfd88041f 2717 #define AES_DATA_IN_5_BASE ((uint8_t)0x8A) /*!< AES engine data input 5 */
group-Avnet 0:478cfd88041f 2718
group-Avnet 0:478cfd88041f 2719 #define AES_DATA_IN_4_BASE ((uint8_t)0x8B) /*!< AES engine data input 4 */
group-Avnet 0:478cfd88041f 2720
group-Avnet 0:478cfd88041f 2721 #define AES_DATA_IN_3_BASE ((uint8_t)0x8C) /*!< AES engine data input 3 */
group-Avnet 0:478cfd88041f 2722
group-Avnet 0:478cfd88041f 2723 #define AES_DATA_IN_2_BASE ((uint8_t)0x8D) /*!< AES engine data input 2 */
group-Avnet 0:478cfd88041f 2724
group-Avnet 0:478cfd88041f 2725 #define AES_DATA_IN_1_BASE ((uint8_t)0x8E) /*!< AES engine data input 1 */
group-Avnet 0:478cfd88041f 2726
group-Avnet 0:478cfd88041f 2727 #define AES_DATA_IN_0_BASE ((uint8_t)0x8F) /*!< AES engine data input 0 */
group-Avnet 0:478cfd88041f 2728
group-Avnet 0:478cfd88041f 2729 /**
group-Avnet 0:478cfd88041f 2730 * @}
group-Avnet 0:478cfd88041f 2731 */
group-Avnet 0:478cfd88041f 2732
group-Avnet 0:478cfd88041f 2733 /** @defgroup AES_DATA_OUT_Register
group-Avnet 0:478cfd88041f 2734 * @{
group-Avnet 0:478cfd88041f 2735 */
group-Avnet 0:478cfd88041f 2736
group-Avnet 0:478cfd88041f 2737 /**
group-Avnet 0:478cfd88041f 2738 * \brief AES_DATA_OUT[15:0] registers
group-Avnet 0:478cfd88041f 2739 * \code
group-Avnet 0:478cfd88041f 2740 * Default value: 0x00
group-Avnet 0:478cfd88041f 2741 * Read
group-Avnet 0:478cfd88041f 2742 *
group-Avnet 0:478cfd88041f 2743 * 7:0 AES_DATA_OUTx[7:0]: AES engine data output (128 bits)
group-Avnet 0:478cfd88041f 2744 * \endcode
group-Avnet 0:478cfd88041f 2745 */
group-Avnet 0:478cfd88041f 2746 #define AES_DATA_OUT_15_BASE ((uint8_t)(0xD4)) /*!< AES engine data output 15 */
group-Avnet 0:478cfd88041f 2747
group-Avnet 0:478cfd88041f 2748 #define AES_DATA_OUT_14_BASE ((uint8_t)(0xD5)) /*!< AES engine data output 14 */
group-Avnet 0:478cfd88041f 2749
group-Avnet 0:478cfd88041f 2750 #define AES_DATA_OUT_13_BASE ((uint8_t)(0xD6)) /*!< AES engine data output 13 */
group-Avnet 0:478cfd88041f 2751
group-Avnet 0:478cfd88041f 2752 #define AES_DATA_OUT_12_BASE ((uint8_t)(0xD7)) /*!< AES engine data output 12 */
group-Avnet 0:478cfd88041f 2753
group-Avnet 0:478cfd88041f 2754 #define AES_DATA_OUT_11_BASE ((uint8_t)(0xD8)) /*!< AES engine data output 11 */
group-Avnet 0:478cfd88041f 2755
group-Avnet 0:478cfd88041f 2756 #define AES_DATA_OUT_10_BASE ((uint8_t)(0xD9)) /*!< AES engine data output 10 */
group-Avnet 0:478cfd88041f 2757
group-Avnet 0:478cfd88041f 2758 #define AES_DATA_OUT_9_BASE ((uint8_t)(0xDA)) /*!< AES engine data output 9 */
group-Avnet 0:478cfd88041f 2759
group-Avnet 0:478cfd88041f 2760 #define AES_DATA_OUT_8_BASE ((uint8_t)(0xDB)) /*!< AES engine data output 8 */
group-Avnet 0:478cfd88041f 2761
group-Avnet 0:478cfd88041f 2762 #define AES_DATA_OUT_7_BASE ((uint8_t)(0xDC)) /*!< AES engine data output 7 */
group-Avnet 0:478cfd88041f 2763
group-Avnet 0:478cfd88041f 2764 #define AES_DATA_OUT_6_BASE ((uint8_t)(0xDD)) /*!< AES engine data output 6 */
group-Avnet 0:478cfd88041f 2765
group-Avnet 0:478cfd88041f 2766 #define AES_DATA_OUT_5_BASE ((uint8_t)(0xDE)) /*!< AES engine data output 5 */
group-Avnet 0:478cfd88041f 2767
group-Avnet 0:478cfd88041f 2768 #define AES_DATA_OUT_4_BASE ((uint8_t)(0xDF)) /*!< AES engine data output 4 */
group-Avnet 0:478cfd88041f 2769
group-Avnet 0:478cfd88041f 2770 #define AES_DATA_OUT_3_BASE ((uint8_t)(0xE0)) /*!< AES engine data output 3 */
group-Avnet 0:478cfd88041f 2771
group-Avnet 0:478cfd88041f 2772 #define AES_DATA_OUT_2_BASE ((uint8_t)(0xE1)) /*!< AES engine data output 2 */
group-Avnet 0:478cfd88041f 2773
group-Avnet 0:478cfd88041f 2774 #define AES_DATA_OUT_1_BASE ((uint8_t)(0xE2)) /*!< AES engine data output 1 */
group-Avnet 0:478cfd88041f 2775
group-Avnet 0:478cfd88041f 2776 #define AES_DATA_OUT_0_BASE ((uint8_t)(0xE3)) /*!< AES engine data output 0 */
group-Avnet 0:478cfd88041f 2777
group-Avnet 0:478cfd88041f 2778 /**
group-Avnet 0:478cfd88041f 2779 * @}
group-Avnet 0:478cfd88041f 2780 */
group-Avnet 0:478cfd88041f 2781
group-Avnet 0:478cfd88041f 2782 /**
group-Avnet 0:478cfd88041f 2783 * @}
group-Avnet 0:478cfd88041f 2784 */
group-Avnet 0:478cfd88041f 2785
group-Avnet 0:478cfd88041f 2786 /** @defgroup IRQ_Registers
group-Avnet 0:478cfd88041f 2787 * @{
group-Avnet 0:478cfd88041f 2788 */
group-Avnet 0:478cfd88041f 2789
group-Avnet 0:478cfd88041f 2790 /** @defgroup IRQ_MASK0_Register
group-Avnet 0:478cfd88041f 2791 * @{
group-Avnet 0:478cfd88041f 2792 */
group-Avnet 0:478cfd88041f 2793
group-Avnet 0:478cfd88041f 2794 /**
group-Avnet 0:478cfd88041f 2795 * \brief IRQ_MASK0 registers
group-Avnet 0:478cfd88041f 2796 * \code
group-Avnet 0:478cfd88041f 2797 * Default value: 0x00
group-Avnet 0:478cfd88041f 2798 * Read Write
group-Avnet 0:478cfd88041f 2799 *
group-Avnet 0:478cfd88041f 2800 * 7:0 INT_MASK0: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
group-Avnet 0:478cfd88041f 2801 *
group-Avnet 0:478cfd88041f 2802 * Bit | Events Group Interrupt Event
group-Avnet 0:478cfd88041f 2803 * -------------------------------------------------------
group-Avnet 0:478cfd88041f 2804 * 0 | RX data ready
group-Avnet 0:478cfd88041f 2805 * 1 | RX data discarded (upon filtering)
group-Avnet 0:478cfd88041f 2806 * 2 | TX data sent
group-Avnet 0:478cfd88041f 2807 * 3 | Max re-TX reached
group-Avnet 0:478cfd88041f 2808 * 4 | CRC error
group-Avnet 0:478cfd88041f 2809 * 5 | TX FIFO underflow/overflow error
group-Avnet 0:478cfd88041f 2810 * 6 | RX FIFO underflow/overflow error
group-Avnet 0:478cfd88041f 2811 * 7 | TX FIFO almost full
group-Avnet 0:478cfd88041f 2812 * \endcode
group-Avnet 0:478cfd88041f 2813 */
group-Avnet 0:478cfd88041f 2814
group-Avnet 0:478cfd88041f 2815
group-Avnet 0:478cfd88041f 2816 #define IRQ_MASK0_BASE ((uint8_t)0x93) /*!< IRQ_MASK is split into 4 registers*/
group-Avnet 0:478cfd88041f 2817
group-Avnet 0:478cfd88041f 2818 #define IRQ_MASK0_RX_DATA_READY ((uint8_t)0x01) /*!< IRQ: RX data ready */
group-Avnet 0:478cfd88041f 2819 #define IRQ_MASK0_RX_DATA_DISC ((uint8_t)0x02) /*!< IRQ: RX data discarded (upon filtering) */
group-Avnet 0:478cfd88041f 2820 #define IRQ_MASK0_TX_DATA_SENT ((uint8_t)0x04) /*!< IRQ: TX data sent */
group-Avnet 0:478cfd88041f 2821 #define IRQ_MASK0_MAX_RE_TX_REACH ((uint8_t)0x08) /*!< IRQ: Max re-TX reached */
group-Avnet 0:478cfd88041f 2822 #define IRQ_MASK0_CRC_ERROR ((uint8_t)0x10) /*!< IRQ: CRC error */
group-Avnet 0:478cfd88041f 2823 #define IRQ_MASK0_TX_FIFO_ERROR ((uint8_t)0x20) /*!< IRQ: TX FIFO underflow/overflow error */
group-Avnet 0:478cfd88041f 2824 #define IRQ_MASK0_RX_FIFO_ERROR ((uint8_t)0x40) /*!< IRQ: RX FIFO underflow/overflow error */
group-Avnet 0:478cfd88041f 2825 #define IRQ_MASK0_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /*!< IRQ: TX FIFO almost full */
group-Avnet 0:478cfd88041f 2826
group-Avnet 0:478cfd88041f 2827 /**
group-Avnet 0:478cfd88041f 2828 * @}
group-Avnet 0:478cfd88041f 2829 */
group-Avnet 0:478cfd88041f 2830
group-Avnet 0:478cfd88041f 2831 /** @defgroup IRQ_MASK1_Register
group-Avnet 0:478cfd88041f 2832 * @{
group-Avnet 0:478cfd88041f 2833 */
group-Avnet 0:478cfd88041f 2834
group-Avnet 0:478cfd88041f 2835 /**
group-Avnet 0:478cfd88041f 2836 * \brief IRQ_MASK1 registers
group-Avnet 0:478cfd88041f 2837 * \code
group-Avnet 0:478cfd88041f 2838 * Default value: 0x00
group-Avnet 0:478cfd88041f 2839 * Read Write
group-Avnet 0:478cfd88041f 2840 *
group-Avnet 0:478cfd88041f 2841 * 7:0 INT_MASK1: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
group-Avnet 0:478cfd88041f 2842 *
group-Avnet 0:478cfd88041f 2843 * Bit | Events Group Interrupt Event
group-Avnet 0:478cfd88041f 2844 * -------------------------------------------------------
group-Avnet 0:478cfd88041f 2845 * 8 | TX FIFO almost empty
group-Avnet 0:478cfd88041f 2846 * 9 | RX FIFO almost full
group-Avnet 0:478cfd88041f 2847 * 10 | RX FIFO almost empty
group-Avnet 0:478cfd88041f 2848 * 11 | Max number of back-off during CCA
group-Avnet 0:478cfd88041f 2849 * 12 | Valid preamble detected
group-Avnet 0:478cfd88041f 2850 * 13 | Sync word detected
group-Avnet 0:478cfd88041f 2851 * 14 | RSSI above threshold (Carrier Sense)
group-Avnet 0:478cfd88041f 2852 * 15 | Wake-up timeout in LDCR mode13
group-Avnet 0:478cfd88041f 2853 * \endcode
group-Avnet 0:478cfd88041f 2854 */
group-Avnet 0:478cfd88041f 2855
group-Avnet 0:478cfd88041f 2856 #define IRQ_MASK1_BASE ((uint8_t)0x92) /*!< IRQ_MASK is split into 4 registers*/
group-Avnet 0:478cfd88041f 2857
group-Avnet 0:478cfd88041f 2858 #define IRQ_MASK1_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /*!< IRQ: TX FIFO almost empty */
group-Avnet 0:478cfd88041f 2859 #define IRQ_MASK1_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /*!< IRQ: RX FIFO almost full */
group-Avnet 0:478cfd88041f 2860 #define IRQ_MASK1_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /*!< IRQ: RX FIFO almost empty */
group-Avnet 0:478cfd88041f 2861 #define IRQ_MASK1_MAX_BO_CCA_REACH ((uint8_t)0x08) /*!< IRQ: Max number of back-off during CCA */
group-Avnet 0:478cfd88041f 2862 #define IRQ_MASK1_VALID_PREAMBLE ((uint8_t)0x10) /*!< IRQ: Valid preamble detected */
group-Avnet 0:478cfd88041f 2863 #define IRQ_MASK1_VALID_SYNC ((uint8_t)0x20) /*!< IRQ: Sync word detected */
group-Avnet 0:478cfd88041f 2864 #define IRQ_MASK1_RSSI_ABOVE_TH ((uint8_t)0x40) /*!< IRQ: RSSI above threshold */
group-Avnet 0:478cfd88041f 2865 #define IRQ_MASK1_WKUP_TOUT_LDC ((uint8_t)0x80) /*!< IRQ: Wake-up timeout in LDC mode */
group-Avnet 0:478cfd88041f 2866
group-Avnet 0:478cfd88041f 2867 /**
group-Avnet 0:478cfd88041f 2868 * @}
group-Avnet 0:478cfd88041f 2869 */
group-Avnet 0:478cfd88041f 2870
group-Avnet 0:478cfd88041f 2871 /** @defgroup IRQ_MASK2_Register
group-Avnet 0:478cfd88041f 2872 * @{
group-Avnet 0:478cfd88041f 2873 */
group-Avnet 0:478cfd88041f 2874
group-Avnet 0:478cfd88041f 2875 /**
group-Avnet 0:478cfd88041f 2876 * \brief IRQ_MASK2 registers
group-Avnet 0:478cfd88041f 2877 * \code
group-Avnet 0:478cfd88041f 2878 * Default value: 0x00
group-Avnet 0:478cfd88041f 2879 * Read Write
group-Avnet 0:478cfd88041f 2880 *
group-Avnet 0:478cfd88041f 2881 * 7:0 INT_MASK2: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
group-Avnet 0:478cfd88041f 2882 *
group-Avnet 0:478cfd88041f 2883 * Bit | Events Group Interrupt Event
group-Avnet 0:478cfd88041f 2884 * -------------------------------------------------------
group-Avnet 0:478cfd88041f 2885 * 16 | READY state in steady condition14
group-Avnet 0:478cfd88041f 2886 * 17 | STANDBY state switching in progress
group-Avnet 0:478cfd88041f 2887 * 18 | Low battery level
group-Avnet 0:478cfd88041f 2888 * 19 | Power-On reset
group-Avnet 0:478cfd88041f 2889 * 20 | Brown-Out event
group-Avnet 0:478cfd88041f 2890 * 21 | LOCK state in steady condition
group-Avnet 0:478cfd88041f 2891 * 22 | PM start-up timer expiration
group-Avnet 0:478cfd88041f 2892 * 23 | XO settling timeout
group-Avnet 0:478cfd88041f 2893 * \endcode
group-Avnet 0:478cfd88041f 2894 */
group-Avnet 0:478cfd88041f 2895 #define IRQ_MASK2_BASE ((uint8_t)0x91) /*!< IRQ_MASK is split into 4 registers*/
group-Avnet 0:478cfd88041f 2896
group-Avnet 0:478cfd88041f 2897 #define IRQ_MASK2_READY ((uint8_t)0x01) /*!< IRQ: READY state */
group-Avnet 0:478cfd88041f 2898 #define IRQ_MASK2_STANDBY_DELAYED ((uint8_t)0x02) /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */
group-Avnet 0:478cfd88041f 2899 #define IRQ_MASK2_LOW_BATT_LVL ((uint8_t)0x04) /*!< IRQ: Battery level below threshold*/
group-Avnet 0:478cfd88041f 2900 #define IRQ_MASK2_POR ((uint8_t)0x08) /*!< IRQ: Power On Reset */
group-Avnet 0:478cfd88041f 2901 #define IRQ_MASK2_BOR ((uint8_t)0x10) /*!< IRQ: Brown out event (both accurate and inaccurate)*/
group-Avnet 0:478cfd88041f 2902 #define IRQ_MASK2_LOCK ((uint8_t)0x20) /*!< IRQ: LOCK state */
group-Avnet 0:478cfd88041f 2903 #define IRQ_MASK2_PM_COUNT_EXPIRED ((uint8_t)0x40) /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */
group-Avnet 0:478cfd88041f 2904 #define IRQ_MASK2_XO_COUNT_EXPIRED ((uint8_t)0x80) /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */
group-Avnet 0:478cfd88041f 2905
group-Avnet 0:478cfd88041f 2906 /**
group-Avnet 0:478cfd88041f 2907 * @}
group-Avnet 0:478cfd88041f 2908 */
group-Avnet 0:478cfd88041f 2909
group-Avnet 0:478cfd88041f 2910 /** @defgroup IRQ_MASK3_Register
group-Avnet 0:478cfd88041f 2911 * @{
group-Avnet 0:478cfd88041f 2912 */
group-Avnet 0:478cfd88041f 2913
group-Avnet 0:478cfd88041f 2914 /**
group-Avnet 0:478cfd88041f 2915 * \brief IRQ_MASK3 registers
group-Avnet 0:478cfd88041f 2916 * \code
group-Avnet 0:478cfd88041f 2917 * Default value: 0x00
group-Avnet 0:478cfd88041f 2918 * Read Write
group-Avnet 0:478cfd88041f 2919 *
group-Avnet 0:478cfd88041f 2920 * 7:0 INT_MASK3: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
group-Avnet 0:478cfd88041f 2921 *
group-Avnet 0:478cfd88041f 2922 * Bit | Events Group Interrupt Event
group-Avnet 0:478cfd88041f 2923 * -------------------------------------------------------
group-Avnet 0:478cfd88041f 2924 * 24 | SYNTH locking timeout
group-Avnet 0:478cfd88041f 2925 * 25 | SYNTH calibration start-up time
group-Avnet 0:478cfd88041f 2926 * 26 | SYNTH calibration timeout
group-Avnet 0:478cfd88041f 2927 * 27 | TX circuitry start-up time
group-Avnet 0:478cfd88041f 2928 * 28 | RX circuitry start-up time
group-Avnet 0:478cfd88041f 2929 * 29 | RX operation timeout
group-Avnet 0:478cfd88041f 2930 * 30 | Others AES End–of –Operation
group-Avnet 0:478cfd88041f 2931 * 31 | Reserved
group-Avnet 0:478cfd88041f 2932 * \endcode
group-Avnet 0:478cfd88041f 2933 */
group-Avnet 0:478cfd88041f 2934 #define IRQ_MASK3_BASE ((uint8_t)0x90) /*!< IRQ_MASK is split into 4 registers*/
group-Avnet 0:478cfd88041f 2935
group-Avnet 0:478cfd88041f 2936 #define IRQ_MASK3_SYNTH_LOCK_TIMEOUT ((uint8_t)0x01) /*!< IRQ: only for debug; LOCK state timeout */
group-Avnet 0:478cfd88041f 2937 #define IRQ_MASK3_SYNTH_LOCK_STARTUP ((uint8_t)0x02) /*!< IRQ: only for debug; see CALIBR_START_COUNTER */
group-Avnet 0:478cfd88041f 2938 #define IRQ_MASK3_SYNTH_CAL_TIMEOUT ((uint8_t)0x04) /*!< IRQ: only for debug; SYNTH calibration timeout */
group-Avnet 0:478cfd88041f 2939 #define IRQ_MASK3_TX_START_TIME ((uint8_t)0x08) /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */
group-Avnet 0:478cfd88041f 2940 #define IRQ_MASK3_RX_START_TIME ((uint8_t)0x10) /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */
group-Avnet 0:478cfd88041f 2941 #define IRQ_MASK3_RX_TIMEOUT ((uint8_t)0x20) /*!< IRQ: RX operation timeout */
group-Avnet 0:478cfd88041f 2942 #define IRQ_MASK3_AES_END ((uint8_t)0x40) /*!< IRQ: AES End of operation */
group-Avnet 0:478cfd88041f 2943
group-Avnet 0:478cfd88041f 2944 /**
group-Avnet 0:478cfd88041f 2945 * @}
group-Avnet 0:478cfd88041f 2946 */
group-Avnet 0:478cfd88041f 2947
group-Avnet 0:478cfd88041f 2948
group-Avnet 0:478cfd88041f 2949 /** @defgroup IRQ_STATUS0_Register
group-Avnet 0:478cfd88041f 2950 * @{
group-Avnet 0:478cfd88041f 2951 */
group-Avnet 0:478cfd88041f 2952
group-Avnet 0:478cfd88041f 2953 /**
group-Avnet 0:478cfd88041f 2954 * \brief IRQ_STATUS0 registers
group-Avnet 0:478cfd88041f 2955 * \code
group-Avnet 0:478cfd88041f 2956 * Default value: 0x00
group-Avnet 0:478cfd88041f 2957 * Read Write
group-Avnet 0:478cfd88041f 2958 *
group-Avnet 0:478cfd88041f 2959 * 7:0 INT_STATUS0: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
group-Avnet 0:478cfd88041f 2960 *
group-Avnet 0:478cfd88041f 2961 * Bit | Events Group Interrupt Event
group-Avnet 0:478cfd88041f 2962 * -------------------------------------------------------
group-Avnet 0:478cfd88041f 2963 * 0 | RX data ready
group-Avnet 0:478cfd88041f 2964 * 1 | RX data discarded (upon filtering)
group-Avnet 0:478cfd88041f 2965 * 2 | TX data sent
group-Avnet 0:478cfd88041f 2966 * 3 | Max re-TX reached
group-Avnet 0:478cfd88041f 2967 * 4 | CRC error
group-Avnet 0:478cfd88041f 2968 * 5 | TX FIFO underflow/overflow error
group-Avnet 0:478cfd88041f 2969 * 6 | RX FIFO underflow/overflow error
group-Avnet 0:478cfd88041f 2970 * 7 | TX FIFO almost full
group-Avnet 0:478cfd88041f 2971 * \endcode
group-Avnet 0:478cfd88041f 2972 */
group-Avnet 0:478cfd88041f 2973
group-Avnet 0:478cfd88041f 2974 #define IRQ_STATUS0_BASE ((uint8_t)(0xFD)) /*!< IRQ Events(RR, split into 4 registers) */
group-Avnet 0:478cfd88041f 2975
group-Avnet 0:478cfd88041f 2976 #define IRQ_STATUS0_SYNTH_LOCK_TIMEOUT ((uint8_t)(0x01)) /*!< IRQ: LOCK state timeout */
group-Avnet 0:478cfd88041f 2977 #define IRQ_STATUS0_SYNTH_LOCK_STARTUP ((uint8_t)(0x02)) /*!< IRQ: only for debug; see CALIBR_START_COUNTER */
group-Avnet 0:478cfd88041f 2978 #define IRQ_STATUS0_SYNTH_CAL_TIMEOUT ((uint8_t)(0x04)) /*!< IRQ: SYNTH locking timeout */
group-Avnet 0:478cfd88041f 2979 #define IRQ_STATUS0_TX_START_TIME ((uint8_t)(0x08)) /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */
group-Avnet 0:478cfd88041f 2980 #define IRQ_STATUS0_RX_START_TIME ((uint8_t)(0x10)) /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */
group-Avnet 0:478cfd88041f 2981 #define IRQ_STATUS0_RX_TIMEOUT ((uint8_t)(0x20)) /*!< IRQ: RX operation timeout expiration */
group-Avnet 0:478cfd88041f 2982 #define IRQ_STATUS0_AES_END ((uint8_t)(0x40)) /*!< IRQ: AES End of operation */
group-Avnet 0:478cfd88041f 2983
group-Avnet 0:478cfd88041f 2984 /**
group-Avnet 0:478cfd88041f 2985 * @}
group-Avnet 0:478cfd88041f 2986 */
group-Avnet 0:478cfd88041f 2987
group-Avnet 0:478cfd88041f 2988 /** @defgroup IRQ_STATUS1_Register
group-Avnet 0:478cfd88041f 2989 * @{
group-Avnet 0:478cfd88041f 2990 */
group-Avnet 0:478cfd88041f 2991
group-Avnet 0:478cfd88041f 2992 /**
group-Avnet 0:478cfd88041f 2993 * \brief IRQ_STATUS1 registers
group-Avnet 0:478cfd88041f 2994 * \code
group-Avnet 0:478cfd88041f 2995 * Default value: 0x00
group-Avnet 0:478cfd88041f 2996 * Read Write
group-Avnet 0:478cfd88041f 2997 *
group-Avnet 0:478cfd88041f 2998 * 7:0 INT_STATUS1: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
group-Avnet 0:478cfd88041f 2999 *
group-Avnet 0:478cfd88041f 3000 * Bit | Events Group Interrupt Event
group-Avnet 0:478cfd88041f 3001 * -------------------------------------------------------
group-Avnet 0:478cfd88041f 3002 * 8 | TX FIFO almost empty
group-Avnet 0:478cfd88041f 3003 * 9 | RX FIFO almost full
group-Avnet 0:478cfd88041f 3004 * 10 | RX FIFO almost empty
group-Avnet 0:478cfd88041f 3005 * 11 | Max number of back-off during CCA
group-Avnet 0:478cfd88041f 3006 * 12 | Valid preamble detected
group-Avnet 0:478cfd88041f 3007 * 13 | Sync word detected
group-Avnet 0:478cfd88041f 3008 * 14 | RSSI above threshold (Carrier Sense)
group-Avnet 0:478cfd88041f 3009 * 15 | Wake-up timeout in LDCR mode13
group-Avnet 0:478cfd88041f 3010 * \endcode
group-Avnet 0:478cfd88041f 3011 */
group-Avnet 0:478cfd88041f 3012
group-Avnet 0:478cfd88041f 3013 #define IRQ_STATUS1_BASE ((uint8_t)(0xFC)) /*!< IRQ Events(RR, split into 4 registers) */
group-Avnet 0:478cfd88041f 3014
group-Avnet 0:478cfd88041f 3015 #define IRQ_STATUS1_READY ((uint8_t)(0x01)) /*!< IRQ: READY state in steady condition*/
group-Avnet 0:478cfd88041f 3016 #define IRQ_STATUS1_STANDBY_DELAYED ((uint8_t)(0x02)) /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */
group-Avnet 0:478cfd88041f 3017 #define IRQ_STATUS1_LOW_BATT_LVL ((uint8_t)(0x04)) /*!< IRQ: Battery level below threshold*/
group-Avnet 0:478cfd88041f 3018 #define IRQ_STATUS1_POR ((uint8_t)(0x08)) /*!< IRQ: Power On Reset */
group-Avnet 0:478cfd88041f 3019 #define IRQ_STATUS1_BOR ((uint8_t)(0x10)) /*!< IRQ: Brown out event (both accurate and inaccurate)*/
group-Avnet 0:478cfd88041f 3020 #define IRQ_STATUS1_LOCK ((uint8_t)(0x20)) /*!< IRQ: LOCK state in steady condition */
group-Avnet 0:478cfd88041f 3021 #define IRQ_STATUS1_PM_COUNT_EXPIRED ((uint8_t)(0x40)) /*!< IRQ: Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */
group-Avnet 0:478cfd88041f 3022 #define IRQ_STATUS1_XO_COUNT_EXPIRED ((uint8_t)(0x80)) /*!< IRQ: Crystal oscillator settling time counter expired */
group-Avnet 0:478cfd88041f 3023
group-Avnet 0:478cfd88041f 3024 /**
group-Avnet 0:478cfd88041f 3025 * @}
group-Avnet 0:478cfd88041f 3026 */
group-Avnet 0:478cfd88041f 3027
group-Avnet 0:478cfd88041f 3028 /** @defgroup IRQ_STATUS2_Register
group-Avnet 0:478cfd88041f 3029 * @{
group-Avnet 0:478cfd88041f 3030 */
group-Avnet 0:478cfd88041f 3031
group-Avnet 0:478cfd88041f 3032 /**
group-Avnet 0:478cfd88041f 3033 * \brief IRQ_STATUS2 registers
group-Avnet 0:478cfd88041f 3034 * \code
group-Avnet 0:478cfd88041f 3035 * Default value: 0x00
group-Avnet 0:478cfd88041f 3036 * Read Write
group-Avnet 0:478cfd88041f 3037 *
group-Avnet 0:478cfd88041f 3038 * 7:0 INT_STATUS2: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
group-Avnet 0:478cfd88041f 3039 *
group-Avnet 0:478cfd88041f 3040 * Bit | Events Group Interrupt Event
group-Avnet 0:478cfd88041f 3041 * -------------------------------------------------------
group-Avnet 0:478cfd88041f 3042 * 16 | READY state in steady condition14
group-Avnet 0:478cfd88041f 3043 * 17 | STANDBY state switching in progress
group-Avnet 0:478cfd88041f 3044 * 18 | Low battery level
group-Avnet 0:478cfd88041f 3045 * 19 | Power-On reset
group-Avnet 0:478cfd88041f 3046 * 20 | Brown-Out event
group-Avnet 0:478cfd88041f 3047 * 21 | LOCK state in steady condition
group-Avnet 0:478cfd88041f 3048 * 22 | PM start-up timer expiration
group-Avnet 0:478cfd88041f 3049 * 23 | XO settling timeout
group-Avnet 0:478cfd88041f 3050 * \endcode
group-Avnet 0:478cfd88041f 3051 */
group-Avnet 0:478cfd88041f 3052
group-Avnet 0:478cfd88041f 3053 #define IRQ_STATUS2_BASE ((uint8_t)0xFB) /*!< IRQ Events(RR, split into 4 registers) */
group-Avnet 0:478cfd88041f 3054
group-Avnet 0:478cfd88041f 3055 #define IRQ_STATUS2_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /*!< IRQ: TX FIFO almost empty */
group-Avnet 0:478cfd88041f 3056 #define IRQ_STATUS2_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /*!< IRQ: RX FIFO almost full */
group-Avnet 0:478cfd88041f 3057 #define IRQ_STATUS2_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /*!< IRQ: RX FIFO almost empty */
group-Avnet 0:478cfd88041f 3058 #define IRQ_STATUS2_MAX_BO_CCA_REACH ((uint8_t)0x08) /*!< IRQ: Max number of back-off during CCA */
group-Avnet 0:478cfd88041f 3059 #define IRQ_STATUS2_VALID_PREAMBLE ((uint8_t)0x10) /*!< IRQ: Valid preamble detected */
group-Avnet 0:478cfd88041f 3060 #define IRQ_STATUS2_VALID_SYNC ((uint8_t)0x20) /*!< IRQ: Sync word detected */
group-Avnet 0:478cfd88041f 3061 #define IRQ_STATUS2_RSSI_ABOVE_TH ((uint8_t)(0x40)) /*!< IRQ: RSSI above threshold */
group-Avnet 0:478cfd88041f 3062 #define IRQ_STATUS2_WKUP_TOUT_LDC ((uint8_t)(0x80)) /*!< IRQ: Wake-up timeout in LDC mode */
group-Avnet 0:478cfd88041f 3063
group-Avnet 0:478cfd88041f 3064 /**
group-Avnet 0:478cfd88041f 3065 * @}
group-Avnet 0:478cfd88041f 3066 */
group-Avnet 0:478cfd88041f 3067
group-Avnet 0:478cfd88041f 3068 /** @defgroup IRQ_STATUS3_Register
group-Avnet 0:478cfd88041f 3069 * @{
group-Avnet 0:478cfd88041f 3070 */
group-Avnet 0:478cfd88041f 3071
group-Avnet 0:478cfd88041f 3072 /**
group-Avnet 0:478cfd88041f 3073 * \brief IRQ_STATUS3 registers
group-Avnet 0:478cfd88041f 3074 * \code
group-Avnet 0:478cfd88041f 3075 * Default value: 0x00
group-Avnet 0:478cfd88041f 3076 * Read Write
group-Avnet 0:478cfd88041f 3077 *
group-Avnet 0:478cfd88041f 3078 * 7:0 INT_STATUS3: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
group-Avnet 0:478cfd88041f 3079 *
group-Avnet 0:478cfd88041f 3080 * Bit | Events Group Interrupt Event
group-Avnet 0:478cfd88041f 3081 * -------------------------------------------------------
group-Avnet 0:478cfd88041f 3082 * 24 | SYNTH locking timeout
group-Avnet 0:478cfd88041f 3083 * 25 | SYNTH calibration start-up time
group-Avnet 0:478cfd88041f 3084 * 26 | SYNTH calibration timeout
group-Avnet 0:478cfd88041f 3085 * 27 | TX circuitry start-up time
group-Avnet 0:478cfd88041f 3086 * 28 | RX circuitry start-up time
group-Avnet 0:478cfd88041f 3087 * 29 | RX operation timeout
group-Avnet 0:478cfd88041f 3088 * 30 | Others AES End–of –Operation
group-Avnet 0:478cfd88041f 3089 * 31 | Reserved
group-Avnet 0:478cfd88041f 3090 * \endcode
group-Avnet 0:478cfd88041f 3091 */
group-Avnet 0:478cfd88041f 3092 #define IRQ_STATUS3_BASE ((uint8_t)0xFA) /*!< IRQ Events(RR, split into 4 registers) */
group-Avnet 0:478cfd88041f 3093
group-Avnet 0:478cfd88041f 3094 #define IRQ_STATUS3_RX_DATA_READY ((uint8_t)0x01) /*!< IRQ: RX data ready */
group-Avnet 0:478cfd88041f 3095 #define IRQ_STATUS3_RX_DATA_DISC ((uint8_t)0x02) /*!< IRQ: RX data discarded (upon filtering) */
group-Avnet 0:478cfd88041f 3096 #define IRQ_STATUS3_TX_DATA_SENT ((uint8_t)0x04) /*!< IRQ: TX data sent */
group-Avnet 0:478cfd88041f 3097 #define IRQ_STATUS3_MAX_RE_TX_REACH ((uint8_t)0x08) /*!< IRQ: Max re-TX reached */
group-Avnet 0:478cfd88041f 3098 #define IRQ_STATUS3_CRC_ERROR ((uint8_t)0x10) /*!< IRQ: CRC error */
group-Avnet 0:478cfd88041f 3099 #define IRQ_STATUS3_TX_FIFO_ERROR ((uint8_t)0x20) /*!< IRQ: TX FIFO underflow/overflow error */
group-Avnet 0:478cfd88041f 3100 #define IRQ_STATUS3_RX_FIFO_ERROR ((uint8_t)0x40) /*!< IRQ: RX FIFO underflow/overflow error */
group-Avnet 0:478cfd88041f 3101 #define IRQ_STATUS3_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /*!< IRQ: TX FIFO almost full */
group-Avnet 0:478cfd88041f 3102
group-Avnet 0:478cfd88041f 3103 /**
group-Avnet 0:478cfd88041f 3104 * @}
group-Avnet 0:478cfd88041f 3105 */
group-Avnet 0:478cfd88041f 3106
group-Avnet 0:478cfd88041f 3107 /**
group-Avnet 0:478cfd88041f 3108 * @}
group-Avnet 0:478cfd88041f 3109 */
group-Avnet 0:478cfd88041f 3110
group-Avnet 0:478cfd88041f 3111
group-Avnet 0:478cfd88041f 3112 /** @defgroup MC_STATE_Registers
group-Avnet 0:478cfd88041f 3113 * @{
group-Avnet 0:478cfd88041f 3114 */
group-Avnet 0:478cfd88041f 3115
group-Avnet 0:478cfd88041f 3116 /** @defgroup MC_STATE1_Register
group-Avnet 0:478cfd88041f 3117 * @{
group-Avnet 0:478cfd88041f 3118 */
group-Avnet 0:478cfd88041f 3119
group-Avnet 0:478cfd88041f 3120 /**
group-Avnet 0:478cfd88041f 3121 * \brief MC_STATE1 registers
group-Avnet 0:478cfd88041f 3122 * \code
group-Avnet 0:478cfd88041f 3123 * Default value: 0x50
group-Avnet 0:478cfd88041f 3124 * Read
group-Avnet 0:478cfd88041f 3125 *
group-Avnet 0:478cfd88041f 3126 * 7:4 Reserved.
group-Avnet 0:478cfd88041f 3127 *
group-Avnet 0:478cfd88041f 3128 * 3 ANT_SELECT: Currently selected antenna
group-Avnet 0:478cfd88041f 3129 *
group-Avnet 0:478cfd88041f 3130 * 2 TX_FIFO_Full: 1 - TX FIFO is full
group-Avnet 0:478cfd88041f 3131 *
group-Avnet 0:478cfd88041f 3132 * 1 RX_FIFO_Empty: 1 - RX FIFO is empty
group-Avnet 0:478cfd88041f 3133 *
group-Avnet 0:478cfd88041f 3134 * 0 ERROR_LOCK: 1 - RCO calibrator error
group-Avnet 0:478cfd88041f 3135 * \endcode
group-Avnet 0:478cfd88041f 3136 */
group-Avnet 0:478cfd88041f 3137 #define MC_STATE1_BASE ((uint8_t)(0xC0)) /*!< MC_STATE1 register address (see the SpiritStatus struct */
group-Avnet 0:478cfd88041f 3138
group-Avnet 0:478cfd88041f 3139
group-Avnet 0:478cfd88041f 3140 /**
group-Avnet 0:478cfd88041f 3141 * @}
group-Avnet 0:478cfd88041f 3142 */
group-Avnet 0:478cfd88041f 3143
group-Avnet 0:478cfd88041f 3144
group-Avnet 0:478cfd88041f 3145 /** @defgroup MC_STATE0_Register
group-Avnet 0:478cfd88041f 3146 * @{
group-Avnet 0:478cfd88041f 3147 */
group-Avnet 0:478cfd88041f 3148
group-Avnet 0:478cfd88041f 3149 /**
group-Avnet 0:478cfd88041f 3150 * \brief MC_STATE0 registers
group-Avnet 0:478cfd88041f 3151 * \code
group-Avnet 0:478cfd88041f 3152 * Default value: 0x00
group-Avnet 0:478cfd88041f 3153 * Read
group-Avnet 0:478cfd88041f 3154 *
group-Avnet 0:478cfd88041f 3155 * 7:1 STATE[6:0]: Current MC state.
group-Avnet 0:478cfd88041f 3156 *
group-Avnet 0:478cfd88041f 3157 * REGISTER VALUE | STATE
group-Avnet 0:478cfd88041f 3158 * --------------------------------------------
group-Avnet 0:478cfd88041f 3159 * 0x40 | STANDBY
group-Avnet 0:478cfd88041f 3160 * 0x36 | SLEEP
group-Avnet 0:478cfd88041f 3161 * 0x03 | READY
group-Avnet 0:478cfd88041f 3162 * 0x3B | PM setup
group-Avnet 0:478cfd88041f 3163 * 0x23 | XO settling
group-Avnet 0:478cfd88041f 3164 * 0x53 | SYNTH setup
group-Avnet 0:478cfd88041f 3165 * 0x1F | PROTOCOL
group-Avnet 0:478cfd88041f 3166 * 0x4F | SYNTH calibration
group-Avnet 0:478cfd88041f 3167 * 0x0F | LOCK
group-Avnet 0:478cfd88041f 3168 * 0x33 | RX
group-Avnet 0:478cfd88041f 3169 * 0x5F | TX
group-Avnet 0:478cfd88041f 3170 *
group-Avnet 0:478cfd88041f 3171 * 0 XO_ON: 1 - XO is operating
group-Avnet 0:478cfd88041f 3172 * \endcode
group-Avnet 0:478cfd88041f 3173 */
group-Avnet 0:478cfd88041f 3174 #define MC_STATE0_BASE ((uint8_t)(0xC1)) /*!< MC_STATE0 register address. In this version ALL existing states have been inserted
group-Avnet 0:478cfd88041f 3175 and are still to be verified */
group-Avnet 0:478cfd88041f 3176 /**
group-Avnet 0:478cfd88041f 3177 * @}
group-Avnet 0:478cfd88041f 3178 */
group-Avnet 0:478cfd88041f 3179
group-Avnet 0:478cfd88041f 3180 /**
group-Avnet 0:478cfd88041f 3181 * @}
group-Avnet 0:478cfd88041f 3182 */
group-Avnet 0:478cfd88041f 3183
group-Avnet 0:478cfd88041f 3184 /** @defgroup Engineering-Test_Registers
group-Avnet 0:478cfd88041f 3185 * @{
group-Avnet 0:478cfd88041f 3186 */
group-Avnet 0:478cfd88041f 3187
group-Avnet 0:478cfd88041f 3188 #define SYNTH_CONFIG1_BASE ((uint8_t)(0x9E)) /*!< Synthesizier registers: M, A, K data sync on positive/negative clock edges [4],
group-Avnet 0:478cfd88041f 3189 Enable Linearization of the charge pump [3], split time 1.75/3.45ns [2], VCO calibration window 16,32,64,128 clock cycles [1:0]*/
group-Avnet 0:478cfd88041f 3190 #define SYNTH_CONFIG0_BASE ((uint8_t)(0x9F)) /*!< Enable DSM randomizer [7], Window width 1.2-7.5ns (Down-up) of lock detector*/
group-Avnet 0:478cfd88041f 3191 #define VCOTH_BASE ((uint8_t)(0xA0)) /*!< Controls the threshold frequency between VCO low and VCO high [7:0]
group-Avnet 0:478cfd88041f 3192 VCOth frequency=2*fXO*(96+VCO_TH/16), fmin=4992 MHz, fmax=5820 MHz*/
group-Avnet 0:478cfd88041f 3193 #define PM_CONFIG2_BASE ((uint8_t)(0xA4)) /*!< Enables high current buffer on Temperature sensor, sets SMPS options */
group-Avnet 0:478cfd88041f 3194 #define PM_CONFIG1_BASE ((uint8_t)(0xA5)) /*!< Set SMPS options */
group-Avnet 0:478cfd88041f 3195 #define PM_CONFIG0_BASE ((uint8_t)(0xA6)) /*!< Set SMPS options */
group-Avnet 0:478cfd88041f 3196 #define VCO_CONFIG_BASE ((uint8_t)(0xA1)) /*!< Set VCO current [5:2]part and [1:0] part */
group-Avnet 0:478cfd88041f 3197 #define XO_CONFIG_BASE ((uint8_t)(0xA7)) /*!< Clock management options from XO to digital part */
group-Avnet 0:478cfd88041f 3198
group-Avnet 0:478cfd88041f 3199 #define XO_RCO_TEST_BASE ((uint8_t)(0xB4)) /*!< Test of XO and RCO */
group-Avnet 0:478cfd88041f 3200
group-Avnet 0:478cfd88041f 3201 /**
group-Avnet 0:478cfd88041f 3202 * @}
group-Avnet 0:478cfd88041f 3203 */
group-Avnet 0:478cfd88041f 3204
group-Avnet 0:478cfd88041f 3205
group-Avnet 0:478cfd88041f 3206 /** @addtogroup Commands
group-Avnet 0:478cfd88041f 3207 * @{
group-Avnet 0:478cfd88041f 3208 */
group-Avnet 0:478cfd88041f 3209
group-Avnet 0:478cfd88041f 3210 #define COMMAND_TX ((uint8_t)(0x60)) /*!< Start to transmit; valid only from READY */
group-Avnet 0:478cfd88041f 3211 #define COMMAND_RX ((uint8_t)(0x61)) /*!< Start to receive; valid only from READY */
group-Avnet 0:478cfd88041f 3212 #define COMMAND_READY ((uint8_t)(0x62)) /*!< Go to READY; valid only from STANDBY or SLEEP or LOCK */
group-Avnet 0:478cfd88041f 3213 #define COMMAND_STANDBY ((uint8_t)(0x63)) /*!< Go to STANDBY; valid only from READY */
group-Avnet 0:478cfd88041f 3214 #define COMMAND_SLEEP ((uint8_t)(0x64)) /*!< Go to SLEEP; valid only from READY */
group-Avnet 0:478cfd88041f 3215 #define COMMAND_LOCKRX ((uint8_t)(0x65)) /*!< Go to LOCK state by using the RX configuration of the synth; valid only from READY */
group-Avnet 0:478cfd88041f 3216 #define COMMAND_LOCKTX ((uint8_t)(0x66)) /*!< Go to LOCK state by using the TX configuration of the synth; valid only from READY */
group-Avnet 0:478cfd88041f 3217 #define COMMAND_SABORT ((uint8_t)(0x67)) /*!< Force exit form TX or RX states and go to READY state; valid only from TX or RX */
group-Avnet 0:478cfd88041f 3218 #define COMMAND_LDC_RELOAD ((uint8_t)(0x68)) /*!< LDC Mode: Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER
group-Avnet 0:478cfd88041f 3219 registers; valid from all states */
group-Avnet 0:478cfd88041f 3220 #define COMMAND_SEQUENCE_UPDATE ((uint8_t)(0x69)) /*!< Autoretransmission: Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register
group-Avnet 0:478cfd88041f 3221 valid from all states */
group-Avnet 0:478cfd88041f 3222 #define COMMAND_AES_ENC ((uint8_t)(0x6A)) /*!< AES: Start the encryption routine; valid from all states; valid from all states */
group-Avnet 0:478cfd88041f 3223 #define COMMAND_AES_KEY ((uint8_t)(0x6B)) /*!< AES: Start the procedure to compute the key for the decryption; valid from all states */
group-Avnet 0:478cfd88041f 3224 #define COMMAND_AES_DEC ((uint8_t)(0x6C)) /*!< AES: Start the decryption routine using the current key; valid from all states */
group-Avnet 0:478cfd88041f 3225 #define COMMAND_AES_KEY_DEC ((uint8_t)(0x6D)) /*!< AES: Compute the key and start the decryption; valid from all states */
group-Avnet 0:478cfd88041f 3226 #define COMMAND_SRES ((uint8_t)(0x70)) /*!< Reset of all digital part, except SPI registers */
group-Avnet 0:478cfd88041f 3227 #define COMMAND_FLUSHRXFIFO ((uint8_t)(0x71)) /*!< Clean the RX FIFO; valid from all states */
group-Avnet 0:478cfd88041f 3228 #define COMMAND_FLUSHTXFIFO ((uint8_t)(0x72)) /*!< Clean the TX FIFO; valid from all states */
group-Avnet 0:478cfd88041f 3229
group-Avnet 0:478cfd88041f 3230 /**
group-Avnet 0:478cfd88041f 3231 * @}
group-Avnet 0:478cfd88041f 3232 */
group-Avnet 0:478cfd88041f 3233
group-Avnet 0:478cfd88041f 3234 /**
group-Avnet 0:478cfd88041f 3235 * @}
group-Avnet 0:478cfd88041f 3236 */
group-Avnet 0:478cfd88041f 3237
group-Avnet 0:478cfd88041f 3238 #ifdef __cplusplus
group-Avnet 0:478cfd88041f 3239 }
group-Avnet 0:478cfd88041f 3240 #endif
group-Avnet 0:478cfd88041f 3241
group-Avnet 0:478cfd88041f 3242 #endif
group-Avnet 0:478cfd88041f 3243
group-Avnet 0:478cfd88041f 3244 /******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/