Analog Devices / ADE120x

Library files for AD1234.

ADE120x.h@3:6c708642886d, 2019-10-22 (annotated)

Committer:
mlambe
Date:
Tue Oct 22 13:22:00 2019 +0000
Revision:
3:6c708642886d
Parent:
2:f9a986799375 
Updated copyright;

Who changed what in which revision?

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mlambe 1:2eb9d6296ec3 1 /**
mlambe 3:6c708642886d 2 @file ADE120x.h
mlambe 3:6c708642886d 3 @brief ADE120x library. This file contains all ADE120x library functions.
mlambe 3:6c708642886d 4 @version V0.0.1
mlambe 3:6c708642886d 5 @author ADI
mlambe 3:6c708642886d 6 @date October 2019
mlambe 3:6c708642886d 7
mlambe 3:6c708642886d 8 Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved.
mlambe 3:6c708642886d 9
mlambe 3:6c708642886d 10 This software is proprietary to Analog Devices, Inc. and its licensors.
mlambe 3:6c708642886d 11 By using this software you agree to the terms of the associated
mlambe 3:6c708642886d 12 Analog Devices Software License Agreement.
mlambe 3:6c708642886d 13 *****************************************************************************/
mlambe 2:f9a986799375 14
mlambe 1:2eb9d6296ec3 15 #ifndef _ADE120x_h_
mlambe 1:2eb9d6296ec3 16 #define _ADE120x_h_
mlambe 1:2eb9d6296ec3 17
mlambe 1:2eb9d6296ec3 18 #include "stdio.h"
mlambe 1:2eb9d6296ec3 19 #include "math.h"
mlambe 1:2eb9d6296ec3 20 #include "string.h"
mlambe 1:2eb9d6296ec3 21 #include <stdint.h>
mlambe 1:2eb9d6296ec3 22
mlambe 1:2eb9d6296ec3 23 #include "mbed.h"
mlambe 1:2eb9d6296ec3 24
mlambe 2:f9a986799375 25
mlambe 2:f9a986799375 26 /**
mlambe 2:f9a986799375 27 * Structure for configuring threshold levels
mlambe 2:f9a986799375 28 */
mlambe 2:f9a986799375 29 typedef struct threshold{
mlambe 2:f9a986799375 30 float BIN_HighThresh; /** Binary channel high threshold */
mlambe 2:f9a986799375 31 float BIN_LowThresh; /** Binary channel low threshold */
mlambe 2:f9a986799375 32 float WARNA_HighThresh; /** WARNA channel high threshold */
mlambe 2:f9a986799375 33 float WARNA_LowThresh; /** WARNA channel Low threshold */
mlambe 2:f9a986799375 34 float WARNB_HighThresh; /** WARNB channel high threshold */
mlambe 2:f9a986799375 35 float WARNB_LowThresh; /** WARNB channel Low threshold */
mlambe 2:f9a986799375 36 float WARNC_HighThresh; /** WARNC channel high threshold */
mlambe 2:f9a986799375 37 float WARNC_LowThresh; /** WARNC channel Low threshold */
mlambe 2:f9a986799375 38 uint8_t BIN_Mode; /** Binary Channel comparator mode */
mlambe 2:f9a986799375 39 uint8_t WARNA_Mode; /** WARNA Channel comparator mode */
mlambe 2:f9a986799375 40 uint8_t WARNB_Mode; /** WARNB Channel comparator mode */
mlambe 2:f9a986799375 41 uint8_t WARNC_Mode; /** WARNC Channel comparator mode */
mlambe 2:f9a986799375 42 uint8_t ADCPga; /** ADC PGA setting */
mlambe 2:f9a986799375 43 float VGain; /** Voltage divider gain */
mlambe 1:2eb9d6296ec3 44 }THRESHCfg_Type;
mlambe 2:f9a986799375 45
mlambe 2:f9a986799375 46 /**
mlambe 2:f9a986799375 47 * Structure for setting programmable load
mlambe 2:f9a986799375 48 */
mlambe 1:2eb9d6296ec3 49 typedef struct{
mlambe 1:2eb9d6296ec3 50 uint8_t enable; /** Enable PL */
mlambe 2:f9a986799375 51 uint8_t mode; /** Configure mode, HIGH_IDLE, LOW_IDLE */
mlambe 2:f9a986799375 52 float HighCurrent; /** High current in mA */
mlambe 1:2eb9d6296ec3 53 float LowCurrent; /** Low current in mA */
mlambe 1:2eb9d6296ec3 54 float HighTime; /** Duration of current pulse in us */
mlambe 1:2eb9d6296ec3 55 float VoltThresh; /** VOltage threshold to trigger programmable load */
mlambe 1:2eb9d6296ec3 56 uint8_t ADCPga; /** ADC PGA setting */
mlambe 2:f9a986799375 57 float VGain; /** Voltage gain set by external resister divider */
mlambe 1:2eb9d6296ec3 58 }PLOADCfg_Type;
mlambe 1:2eb9d6296ec3 59
mlambe 2:f9a986799375 60 /**
mlambe 2:f9a986799375 61 * Structure for configuring energy meter
mlambe 2:f9a986799375 62 */
mlambe 1:2eb9d6296ec3 63 typedef struct{
mlambe 2:f9a986799375 64 uint8_t enable; /** Enable energy meter function */
mlambe 2:f9a986799375 65 float FET_Energy; /** SOA energy of exernal FET used */
mlambe 1:2eb9d6296ec3 66 float PulseMagnitude; /** AMplitude of current pulse in mA */
mlambe 2:f9a986799375 67 float PulseTime; /** Length of current pulse in ms */
mlambe 1:2eb9d6296ec3 68 float WorkingVoltage; /** Working voltage of system in V*/
mlambe 1:2eb9d6296ec3 69 uint32_t AvgADCCode; /** Average ADC code */
mlambe 2:f9a986799375 70 float SampleRate; /** Sample rate, 20us for ADE1202, 10us foe ADE1201 */
mlambe 2:f9a986799375 71 uint8_t Cooldown_TimeStep; /** Set cooldown timestep */
mlambe 2:f9a986799375 72 uint8_t Cooldown_Decr; /* Set cooldown decrement */
mlambe 2:f9a986799375 73 uint8_t Cooldown_Sec; /** Set cooldown period */
mlambe 2:f9a986799375 74 uint8_t Ov_Scale; /** Set over voltage scale factor */
mlambe 2:f9a986799375 75 uint8_t ADCPga; /** ADC PGA setting */
mlambe 2:f9a986799375 76 float VGain; /** Voltage gain set by external resister divider */
mlambe 1:2eb9d6296ec3 77 }EnergyMtrCfg_Type;
mlambe 1:2eb9d6296ec3 78
mlambe 2:f9a986799375 79 /**
mlambe 2:f9a986799375 80 * Data sreuture for reading back register data
mlambe 2:f9a986799375 81 */
mlambe 1:2eb9d6296ec3 82 typedef struct{
mlambe 1:2eb9d6296ec3 83 uint16_t reg_addr;
mlambe 1:2eb9d6296ec3 84 uint32_t reg_data;
mlambe 1:2eb9d6296ec3 85 }RegisterData_Type;
mlambe 1:2eb9d6296ec3 86
mlambe 1:2eb9d6296ec3 87 /******* REGISTER DEFINITION ***********/
mlambe 1:2eb9d6296ec3 88
mlambe 1:2eb9d6296ec3 89 #define REG_LOCK 0x000
mlambe 1:2eb9d6296ec3 90 #define REG_CTRL 0x001
mlambe 1:2eb9d6296ec3 91 #define REG_BIN_CTRL 0x002
mlambe 1:2eb9d6296ec3 92 #define REG_BIN_THR 0x003
mlambe 1:2eb9d6296ec3 93 #define REG_WARNA_THR 0x004
mlambe 1:2eb9d6296ec3 94 #define REG_WARNB_THR 0x005
mlambe 1:2eb9d6296ec3 95 #define REG_WARNC_THR 0x006
mlambe 1:2eb9d6296ec3 96 #define REG_BIN_FILTER 0x007
mlambe 1:2eb9d6296ec3 97 #define REG_WARNA_FILTER 0x008
mlambe 1:2eb9d6296ec3 98 #define REG_WARNB_FILTER 0x009
mlambe 1:2eb9d6296ec3 99 #define REG_WARNC_FILTER 0x00A
mlambe 1:2eb9d6296ec3 100 #define REG_MASK 0x00B
mlambe 1:2eb9d6296ec3 101 #define REG_INT_STATUS 0x00C
mlambe 1:2eb9d6296ec3 102 #define REG_STATUS 0x00D
mlambe 1:2eb9d6296ec3 103 #define REG_ADC 0x00E
mlambe 1:2eb9d6296ec3 104 #define REG_ADCDEC 0x00F
mlambe 1:2eb9d6296ec3 105 #define REG_PL_CTRL 0x010
mlambe 1:2eb9d6296ec3 106 #define REG_PL_RISE_THR 0x011
mlambe 1:2eb9d6296ec3 107 #define REG_PL_LOW_CODE 0x012
mlambe 1:2eb9d6296ec3 108 #define REG_PL_HIGH_CODE 0x013
mlambe 1:2eb9d6296ec3 109 #define REG_PL_HIGH_TIME 0x014
mlambe 1:2eb9d6296ec3 110 #define REG_EGY_MTR_CTRL 0x015
mlambe 1:2eb9d6296ec3 111 #define REG_EGY_MTR_THR 0x016
mlambe 1:2eb9d6296ec3 112 #define REG_EGY_MTR1 0x017
mlambe 1:2eb9d6296ec3 113 #define REG_PL_EN 0x200
mlambe 1:2eb9d6296ec3 114 #define REG_PGA_GAIN 0x201
mlambe 1:2eb9d6296ec3 115
mlambe 1:2eb9d6296ec3 116 /**************************************/
mlambe 1:2eb9d6296ec3 117
mlambe 1:2eb9d6296ec3 118 /******** BIT DEFINITION **************/
mlambe 2:f9a986799375 119 /** Config_LOCK **/
mlambe 2:f9a986799375 120 #define DEV_UNLOCK 0xADE0
mlambe 2:f9a986799375 121 #define DEV_LOCK 0xADE1
mlambe 1:2eb9d6296ec3 122
mlambe 2:f9a986799375 123 /** CTRL **/
mlambe 2:f9a986799375 124 #define DEV_ADE1201 0x0
mlambe 2:f9a986799375 125 #define DEV_ADE1202 0x1000
mlambe 2:f9a986799375 126 #define SW_RST 0x10
mlambe 2:f9a986799375 127 #define ADDR_RELOAD 0x8
mlambe 2:f9a986799375 128 #define ADE1202_IRQ 0x4
mlambe 2:f9a986799375 129 #define CRC_EN 0x1
mlambe 1:2eb9d6296ec3 130
mlambe 2:f9a986799375 131 /** BIN_CTRL **/
mlambe 2:f9a986799375 132 #define Mode_Hysteretic 0
mlambe 2:f9a986799375 133 #define Mode_Inbetween 1
mlambe 2:f9a986799375 134 #define Mode_Greater 2
mlambe 2:f9a986799375 135 #define Mode_LessEqual 3
mlambe 2:f9a986799375 136 #define Decrate_Bypass 0
mlambe 2:f9a986799375 137 #define Decrate_2 1
mlambe 2:f9a986799375 138 #define Decrate_4 2
mlambe 2:f9a986799375 139 #define Decrate_8 3
mlambe 1:2eb9d6296ec3 140
mlambe 2:f9a986799375 141 /** xxx_FILTER **/
mlambe 2:f9a986799375 142 #define Filter_En (1<<15)
mlambe 2:f9a986799375 143 #define Filter_UpDown (1<<14)
mlambe 1:2eb9d6296ec3 144
mlambe 2:f9a986799375 145 /** Interrupt source selection. These sources are defined as bit mask.
mlambe 2:f9a986799375 146 * They are available for register INT_STATUS and STATUS **/
mlambe 1:2eb9d6296ec3 147 #define INTSRC_DOUT1 0x0001 /**< Bit0, DOUT1 */
mlambe 1:2eb9d6296ec3 148 #define INTSRC_WARNA1 0x0002 /**< Bit1, Warning A from channel 1 */
mlambe 1:2eb9d6296ec3 149 #define INTSRC_WARNB1 0x0004 /**< Bit2, Warning B from channel 1 */
mlambe 1:2eb9d6296ec3 150 #define INTSRC_WARNC1 0x0008 /**< Bit3, Warning C from channel 1 */
mlambe 1:2eb9d6296ec3 151 #define INTSRC_DOUT2 0x0010 /**< Bit4, DOUT2 */
mlambe 1:2eb9d6296ec3 152 #define INTSRC_WARNA2 0x0020 /**< Bit5, Warning A from channel 2 */
mlambe 1:2eb9d6296ec3 153 #define INTSRC_WARNB2 0x0040 /**< Bit6, Warning B from channel 2 */
mlambe 1:2eb9d6296ec3 154 #define INTSRC_WARNC2 0x0080 /**< Bit7, Warning C from channel 2 */
mlambe 1:2eb9d6296ec3 155 #define INTSRC_MEMFLT 0x0100 /**< Bit8, Memory fault. After a memory fault is detected the user could reconfigure the device. */
mlambe 1:2eb9d6296ec3 156 #define INTSRC_COMFLT 0x0200 /**< Bit9, Communication fault */
mlambe 1:2eb9d6296ec3 157 #define INTSRC_TSD 0x0400 /**< Bit10, Thermal shutdown detected */
mlambe 1:2eb9d6296ec3 158 #define INTSRC_COOLDOWN1 0x0800 /**< Bit12, Channel 1 is in Cooldown mode */
mlambe 1:2eb9d6296ec3 159 #define INTSRC_COOLDOWN2 0x1000 /**< Bit13, Channel 2 is in Cooldown mode */
mlambe 1:2eb9d6296ec3 160 #define INTSRC_BUSY 0x2000 /**< Bit13, During busy assertion, internal communication is in progress. Once busy is deasserted, an irq can be triggered which indicates normal operation has resumed */
mlambe 1:2eb9d6296ec3 161 #define INTSRC_RSTDONE 0x4000 /**< Bit14, Indicates that the device has reset and is ready to be programmed or begin default normal operation */
mlambe 2:f9a986799375 162 #define INTSRC_ALL 0x7FFF /**< All bits. Used to clear all interrupt sources */
mlambe 2:f9a986799375 163
mlambe 2:f9a986799375 164 /** ADC **/
mlambe 2:f9a986799375 165 #define ADC_RAW 0
mlambe 2:f9a986799375 166 #define ADC_DECIMATOR 1
mlambe 2:f9a986799375 167
mlambe 2:f9a986799375 168 /** PL_CTRL **/
mlambe 2:f9a986799375 169 #define LOW_IDLE 0
mlambe 2:f9a986799375 170 #define HIGH_IDLE 1
mlambe 2:f9a986799375 171
mlambe 2:f9a986799375 172 /** EGY_MTR_CTRL **/
mlambe 2:f9a986799375 173 #define OV_SCALE_1 0
mlambe 2:f9a986799375 174 #define OV_SCALE_4 1
mlambe 2:f9a986799375 175 #define OV_SCALE_8 2
mlambe 2:f9a986799375 176 #define OV_SCALE_16 3
mlambe 2:f9a986799375 177
mlambe 1:2eb9d6296ec3 178
mlambe 2:f9a986799375 179 typedef enum
mlambe 2:f9a986799375 180 {
mlambe 2:f9a986799375 181 COOLDOWN_TS_10us = 0,
mlambe 2:f9a986799375 182 COOLDOWN_TS_20us = 1,
mlambe 2:f9a986799375 183 COOLDOWN_TS_40us = 2,
mlambe 2:f9a986799375 184 COOLDOWN_TS_80us = 3
mlambe 2:f9a986799375 185 }COOLDOWN_TIMESTAMP;
mlambe 2:f9a986799375 186
mlambe 2:f9a986799375 187 #define CH1_Enable 1
mlambe 2:f9a986799375 188 #define CH2_Enable 2
mlambe 2:f9a986799375 189 #define CH1_CH2_Enable 3
mlambe 2:f9a986799375 190 #define CH1_Disable 0
mlambe 2:f9a986799375 191 #define CH2_disable 0
mlambe 2:f9a986799375 192 #define CH1_CH2_Disable 0
mlambe 2:f9a986799375 193
mlambe 2:f9a986799375 194 /** PL_EN **/
mlambe 2:f9a986799375 195 #define PL_CH2_ENABLE (1<<15)
mlambe 2:f9a986799375 196 #define PL_CH1_ENABLE (1<<14)
mlambe 2:f9a986799375 197 #define PL_CH2_DISABLE (0<<15)
mlambe 2:f9a986799375 198 #define PL_CH1_DISABLE (0<<14)
mlambe 2:f9a986799375 199
mlambe 2:f9a986799375 200 /** PGA_GAIN **/
mlambe 2:f9a986799375 201 #define ADCPGA_1 1
mlambe 2:f9a986799375 202 #define ADCPGA_2 3
mlambe 2:f9a986799375 203 #define ADCPGA_5 7
mlambe 2:f9a986799375 204 #define ADCPGA_10 0xF
mlambe 2:f9a986799375 205
mlambe 1:2eb9d6296ec3 206
mlambe 1:2eb9d6296ec3 207 /**
mlambe 1:2eb9d6296ec3 208 * Method to identify ADE120x
mlambe 1:2eb9d6296ec3 209 * [15:14][13:12][11:9] [8:5]
mlambe 1:2eb9d6296ec3 210 * [ RES ][MODEL][Addr][RevIf]
mlambe 1:2eb9d6296ec3 211 *
mlambe 1:2eb9d6296ec3 212 */
mlambe 2:f9a986799375 213 #define ADE120x_Model(data) ((((uint32_t)data)>>12)&0x3) /**< Return model. 0: ADE1201, 1:ADE1202 */
mlambe 2:f9a986799375 214 #define ADE120x_ChipAddr(data) ((((uint32_t)data)>>9)&0x7) /**< Return Chip address*/
mlambe 2:f9a986799375 215 #define ADE120x_RevId(data) ((((uint32_t)data)>>5)&0xf) /**< Return silicon rev ID */
mlambe 1:2eb9d6296ec3 216
mlambe 1:2eb9d6296ec3 217 class ADE120x{
mlambe 1:2eb9d6296ec3 218 public:
mlambe 1:2eb9d6296ec3 219 ADE120x(PinName mosi, PinName miso, PinName sclk, PinName cs);
mlambe 1:2eb9d6296ec3 220
mlambe 1:2eb9d6296ec3 221 void WriteReg(uint8_t addr, uint32_t reg_addr, uint32_t data);
mlambe 1:2eb9d6296ec3 222 uint32_t ReadReg(uint8_t addr, uint32_t reg_addr);
mlambe 1:2eb9d6296ec3 223
mlambe 1:2eb9d6296ec3 224
mlambe 1:2eb9d6296ec3 225 uint8_t Reset(uint8_t addr);
mlambe 1:2eb9d6296ec3 226 uint16_t GetDevID(uint8_t addr);
mlambe 1:2eb9d6296ec3 227 void UnLock(uint8_t addr);
mlambe 1:2eb9d6296ec3 228 void Lock(uint8_t addr);
mlambe 1:2eb9d6296ec3 229 uint8_t DefaultConfig(uint8_t addr);
mlambe 1:2eb9d6296ec3 230
mlambe 1:2eb9d6296ec3 231 void ClearIntStatus(uint8_t addr, uint16_t IntSrcSel);
mlambe 1:2eb9d6296ec3 232 uint16_t GetIntStatus(uint8_t addr);
mlambe 1:2eb9d6296ec3 233 void SetInt(uint8_t addr, uint16_t IntSrcSel);
mlambe 1:2eb9d6296ec3 234
mlambe 1:2eb9d6296ec3 235 void SetBinaryThresh(uint8_t addr, uint16_t thresh);
mlambe 1:2eb9d6296ec3 236 uint8_t CalculateThreshCode(float V_Thresh, uint8_t ADCPga, float V_Gain);
mlambe 1:2eb9d6296ec3 237 uint8_t ThresholdCfg(uint8_t addr, THRESHCfg_Type *pCfg);
mlambe 1:2eb9d6296ec3 238 uint8_t ProgrammableLoadCfg(uint8_t addr, PLOADCfg_Type *pCfg);
mlambe 1:2eb9d6296ec3 239 uint8_t EnergyMtrCfg(uint8_t addr, EnergyMtrCfg_Type *pCfg);
mlambe 1:2eb9d6296ec3 240
mlambe 1:2eb9d6296ec3 241 void SetPgaGain(uint8_t addr, uint16_t gain);
mlambe 1:2eb9d6296ec3 242 uint8_t ReadADC(uint8_t addr, int8_t src);
mlambe 1:2eb9d6296ec3 243 float ADCCode2Volt(uint32_t ADCCode, uint8_t ADCPga, float VOLTAGE_Gain);
mlambe 1:2eb9d6296ec3 244 void GetRegisterData(uint8_t addr, RegisterData_Type *pBuff);
mlambe 1:2eb9d6296ec3 245 private:
mlambe 1:2eb9d6296ec3 246 SPI spi_;
mlambe 1:2eb9d6296ec3 247 DigitalOut nCS_;
mlambe 1:2eb9d6296ec3 248
mlambe 1:2eb9d6296ec3 249 };
mlambe 1:2eb9d6296ec3 250
mlambe 1:2eb9d6296ec3 251 #endif