Akafugu / BurstSPI

BurstSPI fork

Fork of BurstSPI by Erik -

BurstSPI_KL25Z.cpp@14:c99022511536, 2015-04-03 (annotated)

Committer:
Backstrom
Date:
Fri Apr 03 06:14:57 2015 +0000
Revision:
14:c99022511536
Parent:
3:7d9b64d67b22 
As we set receive ignore flag we don't need any code in clearRX.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 3:7d9b64d67b22 1 #ifdef TARGET_KL25Z
Sissors 3:7d9b64d67b22 2 #include "BurstSPI.h"
Sissors 3:7d9b64d67b22 3
Sissors 3:7d9b64d67b22 4 void BurstSPI::fastWrite(int data) {
Sissors 3:7d9b64d67b22 5 //Wait until FIFO has space
Sissors 3:7d9b64d67b22 6 while(((_spi.spi->S) & SPI_S_SPTEF_MASK) == 0);
Sissors 3:7d9b64d67b22 7 //transmit data
Sissors 3:7d9b64d67b22 8 _spi.spi->D = data;
Sissors 3:7d9b64d67b22 9 }
Sissors 3:7d9b64d67b22 10
Sissors 3:7d9b64d67b22 11 void BurstSPI::clearRX( void ) {
Sissors 3:7d9b64d67b22 12 //We put in a delay here, this function shouldn't be called very often, so not a huge problem
Sissors 3:7d9b64d67b22 13 //Without delay you will rise the CS line before it is finished (been there, done that)
Sissors 3:7d9b64d67b22 14 //We use time required to transmit 20 bits (8 bits being transmitted, 8 bits in FIFO, 4 bits safety margin
Sissors 3:7d9b64d67b22 15
Sissors 3:7d9b64d67b22 16 float bytetime = 20.0/_hz;
Sissors 3:7d9b64d67b22 17 wait(bytetime);
Sissors 3:7d9b64d67b22 18
Sissors 3:7d9b64d67b22 19 //Wait until status is flagged that we can read, read:
Sissors 3:7d9b64d67b22 20 while (_spi.spi->S & SPI_S_SPRF_MASK == 0);
Sissors 3:7d9b64d67b22 21 int dummy = _spi.spi->D;
Sissors 3:7d9b64d67b22 22
Sissors 3:7d9b64d67b22 23 }
Sissors 3:7d9b64d67b22 24 #endif