航空研究会
usb実装中
Dependencies: mbed MPU6050_2 HMC5883L_2 SDFileSystem3
MPU9250/MPU9250_register.h@3:c18342e4fddd, 2019-02-06 (annotated)
- Committer:
- Skykon
- Date:
- Wed Feb 06 11:49:05 2019 +0000
- Revision:
- 3:c18342e4fddd
a
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Skykon | 3:c18342e4fddd | 1 | #ifndef MPU9250_REGISTER_H |
| Skykon | 3:c18342e4fddd | 2 | #define MPU9250_REGISTER_H |
| Skykon | 3:c18342e4fddd | 3 | |
| Skykon | 3:c18342e4fddd | 4 | // See also MPU-9250 Register Map and Descriptions, Revision 4.0, RM-MPU-9250A-00, Rev. 1.4, 9/9/2013 for registers not listed in |
| Skykon | 3:c18342e4fddd | 5 | // above document; the MPU9250 and MPU9150 are virtually identical but the latter has a different register map |
| Skykon | 3:c18342e4fddd | 6 | |
| Skykon | 3:c18342e4fddd | 7 | //AK8963 registers |
| Skykon | 3:c18342e4fddd | 8 | #define WHO_AM_I_AK8963 0x00 // should return 0x48 |
| Skykon | 3:c18342e4fddd | 9 | #define INFO 0x01 |
| Skykon | 3:c18342e4fddd | 10 | #define AK8963_ST1 0x02 // data ready status bit 0 |
| Skykon | 3:c18342e4fddd | 11 | #define AK8963_XOUT_L 0x03 // data |
| Skykon | 3:c18342e4fddd | 12 | #define AK8963_XOUT_H 0x04 |
| Skykon | 3:c18342e4fddd | 13 | #define AK8963_YOUT_L 0x05 |
| Skykon | 3:c18342e4fddd | 14 | #define AK8963_YOUT_H 0x06 |
| Skykon | 3:c18342e4fddd | 15 | #define AK8963_ZOUT_L 0x07 |
| Skykon | 3:c18342e4fddd | 16 | #define AK8963_ZOUT_H 0x08 |
| Skykon | 3:c18342e4fddd | 17 | #define AK8963_ST2 0x09 // Data overflow bit 3 and data read error status bit 2 |
| Skykon | 3:c18342e4fddd | 18 | #define AK8963_CNTL 0x0A // Power down (0000), single-measurement (0001), self-test (1000) and Fuse ROM (1111) modes on bits 3:0 |
| Skykon | 3:c18342e4fddd | 19 | #define AK8963_ASTC 0x0C // Self test control |
| Skykon | 3:c18342e4fddd | 20 | #define AK8963_I2CDIS 0x0F // I2C disable |
| Skykon | 3:c18342e4fddd | 21 | #define AK8963_ASAX 0x10 // Fuse ROM x-axis sensitivity adjustment value |
| Skykon | 3:c18342e4fddd | 22 | #define AK8963_ASAY 0x11 // Fuse ROM y-axis sensitivity adjustment value |
| Skykon | 3:c18342e4fddd | 23 | #define AK8963_ASAZ 0x12 // Fuse ROM z-axis sensitivity adjustment value |
| Skykon | 3:c18342e4fddd | 24 | |
| Skykon | 3:c18342e4fddd | 25 | |
| Skykon | 3:c18342e4fddd | 26 | |
| Skykon | 3:c18342e4fddd | 27 | //MPU6500 register |
| Skykon | 3:c18342e4fddd | 28 | #define SELF_TEST_X_GYRO 0x00 |
| Skykon | 3:c18342e4fddd | 29 | #define SELF_TEST_Y_GYRO 0x01 |
| Skykon | 3:c18342e4fddd | 30 | #define SELF_TEST_Z_GYRO 0x02 |
| Skykon | 3:c18342e4fddd | 31 | |
| Skykon | 3:c18342e4fddd | 32 | #define SELF_TEST_X_ACCEL 0x0D |
| Skykon | 3:c18342e4fddd | 33 | #define SELF_TEST_Y_ACCEL 0x0E |
| Skykon | 3:c18342e4fddd | 34 | #define SELF_TEST_Z_ACCEL 0x0F |
| Skykon | 3:c18342e4fddd | 35 | |
| Skykon | 3:c18342e4fddd | 36 | #define SELF_TEST_A 0x10 |
| Skykon | 3:c18342e4fddd | 37 | |
| Skykon | 3:c18342e4fddd | 38 | #define XG_OFFSET_H 0x13 // User-defined trim values for gyroscope |
| Skykon | 3:c18342e4fddd | 39 | #define XG_OFFSET_L 0x14 |
| Skykon | 3:c18342e4fddd | 40 | #define YG_OFFSET_H 0x15 |
| Skykon | 3:c18342e4fddd | 41 | #define YG_OFFSET_L 0x16 |
| Skykon | 3:c18342e4fddd | 42 | #define ZG_OFFSET_H 0x17 |
| Skykon | 3:c18342e4fddd | 43 | #define ZG_OFFSET_L 0x18 |
| Skykon | 3:c18342e4fddd | 44 | #define SMPLRT_DIV 0x19 |
| Skykon | 3:c18342e4fddd | 45 | #define CONFIG 0x1A |
| Skykon | 3:c18342e4fddd | 46 | #define GYRO_CONFIG 0x1B |
| Skykon | 3:c18342e4fddd | 47 | #define ACCEL_CONFIG 0x1C |
| Skykon | 3:c18342e4fddd | 48 | #define ACCEL_CONFIG2 0x1D |
| Skykon | 3:c18342e4fddd | 49 | #define LP_ACCEL_ODR 0x1E |
| Skykon | 3:c18342e4fddd | 50 | #define WOM_THR 0x1F |
| Skykon | 3:c18342e4fddd | 51 | |
| Skykon | 3:c18342e4fddd | 52 | #define MOT_DUR 0x20 // Duration counter threshold for motion interrupt generation, 1 kHz rate, LSB = 1 ms |
| Skykon | 3:c18342e4fddd | 53 | #define ZMOT_THR 0x21 // Zero-motion detection threshold bits [7:0] |
| Skykon | 3:c18342e4fddd | 54 | #define ZRMOT_DUR 0x22 // Duration counter threshold for zero motion interrupt generation, 16 Hz rate, LSB = 64 ms |
| Skykon | 3:c18342e4fddd | 55 | |
| Skykon | 3:c18342e4fddd | 56 | #define FIFO_EN 0x23 |
| Skykon | 3:c18342e4fddd | 57 | #define I2C_MST_CTRL 0x24 |
| Skykon | 3:c18342e4fddd | 58 | #define I2C_SLV0_ADDR 0x25 |
| Skykon | 3:c18342e4fddd | 59 | #define I2C_SLV0_REG 0x26 |
| Skykon | 3:c18342e4fddd | 60 | #define I2C_SLV0_CTRL 0x27 |
| Skykon | 3:c18342e4fddd | 61 | #define I2C_SLV1_ADDR 0x28 |
| Skykon | 3:c18342e4fddd | 62 | #define I2C_SLV1_REG 0x29 |
| Skykon | 3:c18342e4fddd | 63 | #define I2C_SLV1_CTRL 0x2A |
| Skykon | 3:c18342e4fddd | 64 | #define I2C_SLV2_ADDR 0x2B |
| Skykon | 3:c18342e4fddd | 65 | #define I2C_SLV2_REG 0x2C |
| Skykon | 3:c18342e4fddd | 66 | #define I2C_SLV2_CTRL 0x2D |
| Skykon | 3:c18342e4fddd | 67 | #define I2C_SLV3_ADDR 0x2E |
| Skykon | 3:c18342e4fddd | 68 | #define I2C_SLV3_REG 0x2F |
| Skykon | 3:c18342e4fddd | 69 | #define I2C_SLV3_CTRL 0x30 |
| Skykon | 3:c18342e4fddd | 70 | #define I2C_SLV4_ADDR 0x31 |
| Skykon | 3:c18342e4fddd | 71 | #define I2C_SLV4_REG 0x32 |
| Skykon | 3:c18342e4fddd | 72 | #define I2C_SLV4_DO 0x33 |
| Skykon | 3:c18342e4fddd | 73 | #define I2C_SLV4_CTRL 0x34 |
| Skykon | 3:c18342e4fddd | 74 | #define I2C_SLV4_DI 0x35 |
| Skykon | 3:c18342e4fddd | 75 | #define I2C_MST_STATUS 0x36 |
| Skykon | 3:c18342e4fddd | 76 | #define INT_PIN_CFG 0x37 |
| Skykon | 3:c18342e4fddd | 77 | #define INT_ENABLE 0x38 |
| Skykon | 3:c18342e4fddd | 78 | #define DMP_INT_STATUS 0x39 // Check DMP interrupt |
| Skykon | 3:c18342e4fddd | 79 | #define INT_STATUS 0x3A |
| Skykon | 3:c18342e4fddd | 80 | #define ACCEL_XOUT_H 0x3B |
| Skykon | 3:c18342e4fddd | 81 | #define ACCEL_XOUT_L 0x3C |
| Skykon | 3:c18342e4fddd | 82 | #define ACCEL_YOUT_H 0x3D |
| Skykon | 3:c18342e4fddd | 83 | #define ACCEL_YOUT_L 0x3E |
| Skykon | 3:c18342e4fddd | 84 | #define ACCEL_ZOUT_H 0x3F |
| Skykon | 3:c18342e4fddd | 85 | #define ACCEL_ZOUT_L 0x40 |
| Skykon | 3:c18342e4fddd | 86 | #define TEMP_OUT_H 0x41 |
| Skykon | 3:c18342e4fddd | 87 | #define TEMP_OUT_L 0x42 |
| Skykon | 3:c18342e4fddd | 88 | #define GYRO_XOUT_H 0x43 |
| Skykon | 3:c18342e4fddd | 89 | #define GYRO_XOUT_L 0x44 |
| Skykon | 3:c18342e4fddd | 90 | #define GYRO_YOUT_H 0x45 |
| Skykon | 3:c18342e4fddd | 91 | #define GYRO_YOUT_L 0x46 |
| Skykon | 3:c18342e4fddd | 92 | #define GYRO_ZOUT_H 0x47 |
| Skykon | 3:c18342e4fddd | 93 | #define GYRO_ZOUT_L 0x48 |
| Skykon | 3:c18342e4fddd | 94 | #define EXT_SENS_DATA_00 0x49 |
| Skykon | 3:c18342e4fddd | 95 | #define EXT_SENS_DATA_01 0x4A |
| Skykon | 3:c18342e4fddd | 96 | #define EXT_SENS_DATA_02 0x4B |
| Skykon | 3:c18342e4fddd | 97 | #define EXT_SENS_DATA_03 0x4C |
| Skykon | 3:c18342e4fddd | 98 | #define EXT_SENS_DATA_04 0x4D |
| Skykon | 3:c18342e4fddd | 99 | #define EXT_SENS_DATA_05 0x4E |
| Skykon | 3:c18342e4fddd | 100 | #define EXT_SENS_DATA_06 0x4F |
| Skykon | 3:c18342e4fddd | 101 | #define EXT_SENS_DATA_07 0x50 |
| Skykon | 3:c18342e4fddd | 102 | #define EXT_SENS_DATA_08 0x51 |
| Skykon | 3:c18342e4fddd | 103 | #define EXT_SENS_DATA_09 0x52 |
| Skykon | 3:c18342e4fddd | 104 | #define EXT_SENS_DATA_10 0x53 |
| Skykon | 3:c18342e4fddd | 105 | #define EXT_SENS_DATA_11 0x54 |
| Skykon | 3:c18342e4fddd | 106 | #define EXT_SENS_DATA_12 0x55 |
| Skykon | 3:c18342e4fddd | 107 | #define EXT_SENS_DATA_13 0x56 |
| Skykon | 3:c18342e4fddd | 108 | #define EXT_SENS_DATA_14 0x57 |
| Skykon | 3:c18342e4fddd | 109 | #define EXT_SENS_DATA_15 0x58 |
| Skykon | 3:c18342e4fddd | 110 | #define EXT_SENS_DATA_16 0x59 |
| Skykon | 3:c18342e4fddd | 111 | #define EXT_SENS_DATA_17 0x5A |
| Skykon | 3:c18342e4fddd | 112 | #define EXT_SENS_DATA_18 0x5B |
| Skykon | 3:c18342e4fddd | 113 | #define EXT_SENS_DATA_19 0x5C |
| Skykon | 3:c18342e4fddd | 114 | #define EXT_SENS_DATA_20 0x5D |
| Skykon | 3:c18342e4fddd | 115 | #define EXT_SENS_DATA_21 0x5E |
| Skykon | 3:c18342e4fddd | 116 | #define EXT_SENS_DATA_22 0x5F |
| Skykon | 3:c18342e4fddd | 117 | #define EXT_SENS_DATA_23 0x60 |
| Skykon | 3:c18342e4fddd | 118 | #define MOT_DETECT_STATUS 0x61 |
| Skykon | 3:c18342e4fddd | 119 | #define I2C_SLV0_DO 0x63 |
| Skykon | 3:c18342e4fddd | 120 | #define I2C_SLV1_DO 0x64 |
| Skykon | 3:c18342e4fddd | 121 | #define I2C_SLV2_DO 0x65 |
| Skykon | 3:c18342e4fddd | 122 | #define I2C_SLV3_DO 0x66 |
| Skykon | 3:c18342e4fddd | 123 | #define I2C_MST_DELAY_CTRL 0x67 |
| Skykon | 3:c18342e4fddd | 124 | #define SIGNAL_PATH_RESET 0x68 |
| Skykon | 3:c18342e4fddd | 125 | #define MOT_DETECT_CTRL 0x69 |
| Skykon | 3:c18342e4fddd | 126 | #define USER_CTRL 0x6A // Bit 7 enable DMP, bit 3 reset DMP |
| Skykon | 3:c18342e4fddd | 127 | #define PWR_MGMT_1 0x6B // Device defaults to the SLEEP mode |
| Skykon | 3:c18342e4fddd | 128 | #define PWR_MGMT_2 0x6C |
| Skykon | 3:c18342e4fddd | 129 | #define DMP_BANK 0x6D // Activates a specific bank in the DMP |
| Skykon | 3:c18342e4fddd | 130 | #define DMP_RW_PNT 0x6E // Set read/write pointer to a specific start address in specified DMP bank |
| Skykon | 3:c18342e4fddd | 131 | #define DMP_REG 0x6F // Register in DMP from which to read or to which to write |
| Skykon | 3:c18342e4fddd | 132 | #define DMP_REG_1 0x70 |
| Skykon | 3:c18342e4fddd | 133 | #define DMP_REG_2 0x71 |
| Skykon | 3:c18342e4fddd | 134 | #define FIFO_COUNTH 0x72 |
| Skykon | 3:c18342e4fddd | 135 | #define FIFO_COUNTL 0x73 |
| Skykon | 3:c18342e4fddd | 136 | #define FIFO_R_W 0x74 |
| Skykon | 3:c18342e4fddd | 137 | #define WHO_AM_I_MPU9250 0x75 // Should return 0x71 |
| Skykon | 3:c18342e4fddd | 138 | #define XA_OFFSET_H 0x77 |
| Skykon | 3:c18342e4fddd | 139 | #define XA_OFFSET_L 0x78 |
| Skykon | 3:c18342e4fddd | 140 | #define YA_OFFSET_H 0x7A |
| Skykon | 3:c18342e4fddd | 141 | #define YA_OFFSET_L 0x7B |
| Skykon | 3:c18342e4fddd | 142 | #define ZA_OFFSET_H 0x7D |
| Skykon | 3:c18342e4fddd | 143 | #define ZA_OFFSET_L 0x7E |
| Skykon | 3:c18342e4fddd | 144 | |
| Skykon | 3:c18342e4fddd | 145 | #endif |