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8 years, 9 months ago.
What is the Mbed maximum SPI clock frequency?
Hi everyone, I use one channel 24 Bits ADC for my project. And i try to calculate maximum data rates of an ADC that it can reach up. So my question is related with SPI clock frequency. For example, ADC gets one bit data in every SPI clock pulse. So if i have 24 bit ADC, i need 24 clock pulse for one ADC conversion. If ADC data rate is 1 Msps, i need 24 Mega clock pulse. Thus i need at least 24 MHz SPI clock frequency. And if i have 4 channels simultaneous ADC, SPI frequency should 4*24=96 MHz. However Mbed has a 96 MHz microprocessor. So SPI frequency can not be 96 MHz. What is the maximum SPI clock frequncy that Mbed reach up?
1 Answer
8 years, 9 months ago.
48MHz on the LPC1768. However the mbed library has significant overhead at those speeds. There are libs for faster writing, but I don't need about reading. Also have you considered how you are going to process all that data? And do you really need that much resolution at that speed? Also for sure you are going to want to use multiple SPI busses in parallel.
You will need to directly access MCU registers to make this work. And DMA might depending on the exact requirements also needed
Thank you for quick reply. I did not think how am i process all data. Actually, i don't need that resolution at 1 Msps. However, as my design, i try to use 8 ADC (Max11040K) in Cascadable Mode with Simultaneous Sampling. I want to use only one SPI bus for all ADCs. So, 8 ADC x 4 channel (each of ADC has 4 channels) x 24 bits x data rates must be lower than 48 MHz. So that 768 x Data rates < 96 MHz. And data rate < 125 Ksps theoretically. Is my calculation correct? Actually i want to learn maximum limitations if i use Mbed. Note: I have consider Max11040K has maximum 64 Ksps data rate. For my questions, you assume that there is an ADC that reaches higher data rates.
posted by 14 Jul 2015Hi Erik, Do you have another idea for my last comment? I wonder your explanations.
posted by 20 Jul 2015I think you should mainly consider also what kind of data processing you are going to do on it: Just getting the data on the MCU won't be sufficient.
The SPI can't handle more than 48MHz, you did your calculations with 96MHz, so you should divide the end result by two: Per SPI bus you can ideally sample at 62.5kHz. Then there is also the question about overhead: Do CS pins need to be toggled for example? Or can you just continiously stream data from the ADCs?
(Note that you can also clock your LPC1768 higher, 100MHz is supported, higher probably works. If you want to be sure you can get LPC1769 which is identical, only rated to 120MHz. But then you don't have the mbed board).
posted by 20 Jul 2015
Unless the ADC also supports 100MHz SPI multiple buses will be a requirement no matter what the mbed can do.
To be honest I think you need to either relax your requirements a little or look at something other than mbed. A 24bit ADC that can do 1Ms/s isn't going to be the cheapest product in the world. In order for anything beyond the 16th bit to be anything other than a random number generator you need to have some fairly careful PCB design, if you are looking to use 4 of them then you are either making a custom PCB or using a lot of demo kits strapped together, this isn't something you could knock up on some breadboard. In that situation you can probably afford a CPU with a little more processing power behind it than an mbed.
posted by Andy A 14 Jul 2015Really thank you for your advices and reply. I know there is no 24 bit 1 Ms/s ADC but i have 32 channels at 24 bit in my design. So i think that i should consider Mbed SPI bus limitations. Do you have another advice or idea (or component) compatible with Mbed and 32 simultaneous channel ADCs?
posted by cem mortaş 14 Jul 2015