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NXP/K82F/flash_config.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2018 ARM Limited
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 #ifndef MBED_QSPI_FLASH_CONFIG_H
18 #define MBED_QSPI_FLASH_CONFIG_H
19 
20 #include "../../MX25RXX35F_config.h"
21 
22 /* Fast mode not supported in MX25U3235F */
23 #undef FAST_MODE_ENABLE
24 #undef FAST_MODE_DISABLE
25 
26 #ifdef QSPI_SECTOR_COUNT
27 #undef QSPI_SECTOR_COUNT
28 #define QSPI_SECTOR_COUNT 1024 // for MX25U3235F
29 #endif
30 
31 /* The values for MX25U3235F are different, specify this here */
32 #undef QSPI_COMMON_MAX_FREQUENCY
33 #undef QSPI_WRSR_MAX_TIME
34 #undef QSPI_PAGE_PROG_MAX_TIME
35 #undef QSPI_ERASE_SECTOR_MAX_TIME
36 #undef QSPI_ERASE_BLOCK_32_MAX_TIME
37 #undef QSPI_ERASE_BLOCK_64_MAX_TIME
38 
39 /* Implementation of these macros are slightly different for MX25U3235F */
40 #undef EXTENDED_SPI_ENABLE
41 #undef EXTENDED_SPI_DISABLE
42 
43 /* Max frequency for basic rw operation in MX25U3235F */
44 #define QSPI_COMMON_MAX_FREQUENCY 54000000
45 
46 /* WRSR operations max time [us] (datasheet max time + 15%) */
47 #define QSPI_WRSR_MAX_TIME 46000 // 40ms
48 
49 /* Write operations max time [us] (datasheet max time + 15%) */
50 #define QSPI_PAGE_PROG_MAX_TIME 3450 // 3ms
51 
52 /* erase operations max time [us] (datasheet max time + 15%) */
53 #define QSPI_ERASE_SECTOR_MAX_TIME 230000 // 200 ms
54 #define QSPI_ERASE_BLOCK_32_MAX_TIME 1150000 // 1s
55 #define QSPI_ERASE_BLOCK_64_MAX_TIME 2300000 // 2s
56 
57 #define EXTENDED_SPI_ENABLE() \
58  \
59  const int32_t reg_size = QSPI_STATUS_REG_SIZE; \
60  uint8_t reg_data[reg_size] = { 0 }; \
61  \
62  if (read_register(STATUS_REG, reg_data, \
63  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
64  return QSPI_STATUS_ERROR; \
65  } \
66  if (write_enable(qspi) != QSPI_STATUS_OK) { \
67  return QSPI_STATUS_ERROR; \
68  } \
69  \
70  reg_data[0] = STATUS_BIT_QE; \
71  if (write_register(QSPI_CMD_WRSR, reg_data, \
72  reg_size, qspi) != QSPI_STATUS_OK) { \
73  return QSPI_STATUS_ERROR; \
74  } \
75  WAIT_FOR(WRSR_MAX_TIME, qspi); \
76  \
77  memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
78  if (read_register(STATUS_REG, reg_data, \
79  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
80  return QSPI_STATUS_ERROR; \
81  } \
82  \
83  return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
84  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
85 
86 
87 
88 #define EXTENDED_SPI_DISABLE() \
89  \
90  const int32_t reg_size = QSPI_STATUS_REG_SIZE; \
91  uint8_t reg_data[reg_size] = { 0 }; \
92  \
93  if (read_register(STATUS_REG, reg_data, \
94  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
95  return QSPI_STATUS_ERROR; \
96  } \
97  \
98  if (write_enable(qspi) != QSPI_STATUS_OK) { \
99  return QSPI_STATUS_ERROR; \
100  } \
101  \
102  reg_data[0] &= ~(STATUS_BIT_QE); \
103  \
104  if (write_register(QSPI_CMD_WRSR, reg_data, \
105  reg_size, qspi) != QSPI_STATUS_OK) { \
106  return QSPI_STATUS_ERROR; \
107  } \
108  WAIT_FOR(WRSR_MAX_TIME, qspi); \
109  \
110  reg_data[0] = 0; \
111  if (read_register(STATUS_REG, reg_data, \
112  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
113  return QSPI_STATUS_ERROR; \
114  } \
115  \
116  return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
117  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
118 
119 #endif // MBED_QSPI_FLASH_CONFIG_H
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