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shci.h
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1 /**
2  ******************************************************************************
3  * @file shci.h
4  * @author MCD Application Team
5  * @brief HCI command for the system channel
6  ******************************************************************************
7  * @attention
8  *
9  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
10  * All rights reserved.</center></h2>
11  *
12  * This software component is licensed by ST under BSD 3-Clause license,
13  * the "License"; You may not use this file except in compliance with the
14  * License. You may obtain a copy of the License at:
15  * opensource.org/licenses/BSD-3-Clause
16  *
17  ******************************************************************************
18  */
19 
20 
21 /* Define to prevent recursive inclusion -------------------------------------*/
22 #ifndef __SHCI_H
23 #define __SHCI_H
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
29  /* Includes ------------------------------------------------------------------*/
30 #include "mbox_def.h" /* Requested to expose the MB_WirelessFwInfoTable_t structure */
31 
32  /* Exported types ------------------------------------------------------------*/
33 
34  /* SYSTEM EVENT */
35  typedef enum
36  {
37  WIRELESS_FW_RUNNING = 0x00,
38  RSS_FW_RUNNING = 0x01,
39  } SHCI_SysEvt_Ready_Rsp_t;
40 
41  /* ERROR CODES
42  *
43  * These error codes are detected on M0 side and are send back to the M4 via a system
44  * notification message. It is up to the application running on M4 to manage these errors
45  *
46  * These errors can be generated by all layers (low level driver, stack, framework infrastructure, etc..)
47  */
48  typedef enum
49  {
50  ERR_BLE_INIT = 0,
51  ERR_THREAD_LLD_FATAL_ERROR = 125, /* The LLD driver used on 802_15_4 detected a fatal error */
52  ERR_THREAD_UNKNOWN_CMD = 126, /* The command send by the M4 to control the Thread stack is unknown */
53  ERR_ZIGBEE_UNKNOWN_CMD = 200, /* The command send by the M4 to control the Zigbee stack is unknown */
54  } SCHI_SystemErrCode_t;
55 
56 #define SHCI_EVTCODE ( 0xFF )
57 #define SHCI_SUB_EVT_CODE_BASE ( 0x9200 )
58 
59  /**
60  * THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU1 DEFINITION
61  */
62  typedef enum
63  {
64  SHCI_SUB_EVT_CODE_READY = SHCI_SUB_EVT_CODE_BASE,
65  SHCI_SUB_EVT_ERROR_NOTIF,
67 
68  typedef PACKED_STRUCT{
69  SHCI_SysEvt_Ready_Rsp_t sysevt_ready_rsp;
70  } SHCI_C2_Ready_Evt_t;
71 
72  typedef PACKED_STRUCT{
73  SCHI_SystemErrCode_t errorCode;
74  } SHCI_C2_ErrorNotif_Evt_t;
75 
76  /* SYSTEM COMMAND */
77  typedef PACKED_STRUCT
78  {
79  uint32_t MetaData[3];
80  } SHCI_Header_t;
81 
82  typedef enum
83  {
84  SHCI_Success = 0x00,
85  SHCI_UNKNOWN_CMD = 0x01,
86  SHCI_ERR_UNSUPPORTED_FEATURE = 0x11,
87  SHCI_ERR_INVALID_HCI_CMD_PARAMS = 0x12,
88  SHCI_FUS_CMD_NOT_SUPPORTED = 0xFF,
89  } SHCI_CmdStatus_t;
90 
91  typedef enum
92  {
93  SHCI_8BITS = 0x01,
94  SHCI_16BITS = 0x02,
95  SHCI_32BITS = 0x04,
96  } SHCI_Busw_t;
97 
98 #define SHCI_OGF ( 0x3F )
99 #define SHCI_OCF_BASE ( 0x50 )
100 
101  /**
102  * THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU2 DEFINITION
103  */
104  typedef enum
105  {
106  SHCI_OCF_C2_RESERVED1 = SHCI_OCF_BASE,
107  SHCI_OCF_C2_RESERVED2,
108  SHCI_OCF_C2_FUS_GET_STATE,
109  SHCI_OCF_C2_FUS_RESERVED1,
110  SHCI_OCF_C2_FUS_FW_UPGRADE,
111  SHCI_OCF_C2_FUS_FW_DELETE,
112  SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY,
113  SHCI_OCF_C2_FUS_LOCK_AUTH_KEY,
114  SHCI_OCF_C2_FUS_STORE_USR_KEY,
115  SHCI_OCF_C2_FUS_LOAD_USR_KEY,
116  SHCI_OCF_C2_FUS_START_WS,
117  SHCI_OCF_C2_FUS_RESERVED2,
118  SHCI_OCF_C2_FUS_RESERVED3,
119  SHCI_OCF_C2_FUS_LOCK_USR_KEY,
120  SHCI_OCF_C2_FUS_RESERVED5,
121  SHCI_OCF_C2_FUS_RESERVED6,
122  SHCI_OCF_C2_FUS_RESERVED7,
123  SHCI_OCF_C2_FUS_RESERVED8,
124  SHCI_OCF_C2_FUS_RESERVED9,
125  SHCI_OCF_C2_FUS_RESERVED10,
126  SHCI_OCF_C2_FUS_RESERVED11,
127  SHCI_OCF_C2_FUS_RESERVED12,
128  SHCI_OCF_C2_BLE_INIT,
129  SHCI_OCF_C2_THREAD_INIT,
130  SHCI_OCF_C2_DEBUG_INIT,
131  SHCI_OCF_C2_FLASH_ERASE_ACTIVITY,
132  SHCI_OCF_C2_CONCURRENT_SET_MODE,
133  SHCI_OCF_C2_FLASH_STORE_DATA,
134  SHCI_OCF_C2_FLASH_ERASE_DATA,
135  SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER,
136  SHCI_OCF_C2_MAC_802_15_4_INIT,
137  SHCI_OCF_C2_REINIT,
138  SHCI_OCF_C2_ZIGBEE_INIT,
139  SHCI_OCF_C2_LLD_TESTS_INIT,
140  SHCI_OCF_C2_EXTPA_CONFIG,
141  SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL,
142  SHCI_OCF_C2_LLD_BLE_INIT
143  } SHCI_OCF_t;
144 
145 #define SHCI_OPCODE_C2_FUS_GET_STATE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE)
146 /** No command parameters */
147 /** Response parameters*/
148  typedef enum
149  {
150  FUS_STATE_NO_ERROR = 0x00,
151  FUS_STATE_IMG_NOT_FOUND = 0x01,
152  FUS_STATE_IMG_CORRUPT = 0x02,
153  FUS_STATE_IMG_NOT_AUTHENTIC = 0x03,
154  FUS_STATE_IMG_NOT_ENOUGH_SPACE = 0x04,
155  FUS_STATE_ERR_UNKNOWN = 0xFF,
157 
158 #define SHCI_OPCODE_C2_FUS_RESERVED1 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED1)
159 /** No command parameters */
160 /** No response parameters*/
161 
162 #define SHCI_OPCODE_C2_FUS_FW_UPGRADE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_UPGRADE)
163  /** No structure for command parameters */
164  /** No response parameters*/
165 
166 #define SHCI_OPCODE_C2_FUS_FW_DELETE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_DELETE)
167 /** No command parameters */
168 /** No response parameters*/
169 
170 #define SHCI_OPCODE_C2_FUS_UPDATE_AUTH_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY)
171  typedef PACKED_STRUCT{
172  uint8_t KeySize;
173  uint8_t KeyData[64];
174  } SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t;
175 
176  /** No response parameters*/
177 
178 #define SHCI_OPCODE_C2_FUS_LOCK_AUTH_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_AUTH_KEY)
179 /** No command parameters */
180 /** No response parameters*/
181 
182 #define SHCI_OPCODE_C2_FUS_STORE_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_STORE_USR_KEY)
183  /** Command parameters */
184  /* List of supported key type */
185  enum
186  {
187  KEYTYPE_NONE = 0x00,
188  KEYTYPE_SIMPLE = 0x01,
189  KEYTYPE_MASTER = 0x02,
190  KEYTYPE_ENCRYPTED = 0x03,
191  };
192 
193  /* List of supported key size */
194  enum
195  {
196  KEYSIZE_16 = 16,
197  KEYSIZE_32 = 32,
198  };
199 
200  typedef PACKED_STRUCT{
201  uint8_t KeyType;
202  uint8_t KeySize;
203  uint8_t KeyData[32 + 12];
204  } SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t;
205 
206  /** Response parameters*/
207  /** It responds a 1 byte value holding the index given for the stored key */
208 
209 #define SHCI_OPCODE_C2_FUS_LOAD_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOAD_USR_KEY)
210  /** Command parameters */
211  /** 1 byte holding the key index value */
212 
213  /** No response parameters*/
214 
215 #define SHCI_OPCODE_C2_FUS_START_WS (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_START_WS)
216 /** No command parameters */
217 /** No response parameters*/
218 
219 #define SHCI_OPCODE_C2_FUS_RESERVED2 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED2)
220 /** No command parameters */
221 /** No response parameters*/
222 
223 #define SHCI_OPCODE_C2_FUS_RESERVED3 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED3)
224 /** No command parameters */
225 /** No response parameters*/
226 
227 #define SHCI_OPCODE_C2_FUS_LOCK_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_USR_KEY)
228  /** Command parameters */
229  /** 1 byte holding the key index value */
230 
231  /** No response parameters*/
232 
233 #define SHCI_OPCODE_C2_FUS_RESERVED5 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED5)
234 /** No command parameters */
235 /** No response parameters*/
236 
237 #define SHCI_OPCODE_C2_FUS_RESERVED6 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED6)
238 /** No command parameters */
239 /** No response parameters*/
240 
241 #define SHCI_OPCODE_C2_FUS_RESERVED7 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED7)
242 /** No command parameters */
243 /** No response parameters*/
244 
245 #define SHCI_OPCODE_C2_FUS_RESERVED8 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED8)
246 /** No command parameters */
247 /** No response parameters*/
248 
249 #define SHCI_OPCODE_C2_FUS_RESERVED9 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED9)
250 /** No command parameters */
251 /** No response parameters*/
252 
253 #define SHCI_OPCODE_C2_FUS_RESERVED10 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED10)
254 /** No command parameters */
255 /** No response parameters*/
256 
257 #define SHCI_OPCODE_C2_FUS_RESERVED11 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED11)
258 /** No command parameters */
259 /** No response parameters*/
260 
261 #define SHCI_OPCODE_C2_FUS_RESERVED12 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED12)
262 /** No command parameters */
263 /** No response parameters*/
264 
265 #define SHCI_OPCODE_C2_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_INIT)
266  /** THE ORDER SHALL NOT BE CHANGED */
267  typedef PACKED_STRUCT{
268  uint8_t* pBleBufferAddress; /**< NOT USED CURRENTLY */
269  uint32_t BleBufferSize; /**< Size of the Buffer allocated in pBleBufferAddress */
270  uint16_t NumAttrRecord;
271  uint16_t NumAttrServ;
272  uint16_t AttrValueArrSize;
273  uint8_t NumOfLinks;
274  uint8_t ExtendedPacketLengthEnable;
275  uint8_t PrWriteListSize;
276  uint8_t MblockCount;
277  uint16_t AttMtu;
278  uint16_t SlaveSca;
279  uint8_t MasterSca;
280  uint8_t LsSource;
281  uint32_t MaxConnEventLength;
282  uint16_t HsStartupTime;
283  uint8_t ViterbiEnable;
284  uint8_t LlOnly;
285  uint8_t HwVersion;
286  } SHCI_C2_Ble_Init_Cmd_Param_t;
287 
288  typedef PACKED_STRUCT{
289  SHCI_Header_t Header; /** Does not need to be initialized by the user */
290  SHCI_C2_Ble_Init_Cmd_Param_t Param;
291  } SHCI_C2_Ble_Init_Cmd_Packet_t;
292 
293  /** No response parameters*/
294 
295 #define SHCI_OPCODE_C2_THREAD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_THREAD_INIT)
296 /** No command parameters */
297 /** No response parameters*/
298 
299 #define SHCI_OPCODE_C2_DEBUG_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_DEBUG_INIT)
300  /** Command parameters */
301  typedef PACKED_STRUCT
302  {
303  uint8_t thread_config;
304  uint8_t ble_config;
305  uint8_t mac_802_15_4_config;
306  uint8_t zigbee_config;
307  } SHCI_C2_DEBUG_TracesConfig_t;
308 
309  typedef PACKED_STRUCT
310  {
311  uint8_t ble_dtb_cfg;
312  uint8_t reserved[3];
313  } SHCI_C2_DEBUG_GeneralConfig_t;
314 
315  typedef PACKED_STRUCT{
316  uint8_t *pGpioConfig;
317  uint8_t *pTracesConfig;
318  uint8_t *pGeneralConfig;
319  uint8_t GpioConfigSize;
320  uint8_t TracesConfigSize;
321  uint8_t GeneralConfigSize;
322  } SHCI_C2_DEBUG_init_Cmd_Param_t;
323 
324  typedef PACKED_STRUCT{
325  SHCI_Header_t Header; /** Does not need to be initialized by the user */
326  SHCI_C2_DEBUG_init_Cmd_Param_t Param;
327  } SHCI_C2_DEBUG_Init_Cmd_Packet_t;
328  /** No response parameters*/
329 
330 #define SHCI_OPCODE_C2_FLASH_ERASE_ACTIVITY (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_ACTIVITY)
331  /** Command parameters */
332  typedef enum
333  {
334  ERASE_ACTIVITY_OFF = 0x00,
335  ERASE_ACTIVITY_ON = 0x01,
337 
338  /** No response parameters*/
339 
340 #define SHCI_OPCODE_C2_CONCURRENT_SET_MODE (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_SET_MODE)
341 /** command parameters */
342  typedef enum
343  {
344  BLE_ENABLE,
345  THREAD_ENABLE,
346  ZIGBEE_ENABLE,
348  /** No response parameters*/
349 
350 #define SHCI_OPCODE_C2_FLASH_STORE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_STORE_DATA)
351 #define SHCI_OPCODE_C2_FLASH_ERASE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_DATA)
352 /** command parameters */
353  typedef enum
354  {
355  BLE_IP,
356  THREAD_IP,
357  ZIGBEE_IP,
359  /** No response parameters*/
360 
361 #define SHCI_OPCODE_C2_RADIO_ALLOW_LOW_POWER (( SHCI_OGF << 10) + SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER)
362 
363 #define SHCI_OPCODE_C2_MAC_802_15_4_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_MAC_802_15_4_INIT)
364 
365 #define SHCI_OPCODE_C2_REINIT (( SHCI_OGF << 10) + SHCI_OCF_C2_REINIT)
366 
367 #define SHCI_OPCODE_C2_ZIGBEE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_ZIGBEE_INIT)
368 
369 #define SHCI_OPCODE_C2_LLD_TESTS_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_TESTS_INIT)
370 
371 #define SHCI_OPCODE_C2_LLD_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_BLE_INIT)
372 
373 #define SHCI_OPCODE_C2_EXTPA_CONFIG (( SHCI_OGF << 10) + SHCI_OCF_C2_EXTPA_CONFIG)
374  /** Command parameters */
375  enum
376  {
377  EXT_PA_ENABLED_LOW,
378  EXT_PA_ENABLED_HIGH,
379  }/* gpio_polarity */;
380 
381  enum
382  {
383  EXT_PA_DISABLED,
384  EXT_PA_ENABLED,
385  }/* gpio_status */;
386 
387  typedef PACKED_STRUCT{
388  uint32_t gpio_port;
389  uint16_t gpio_pin_number;
390  uint8_t gpio_polarity;
391  uint8_t gpio_status;
392  } SHCI_C2_EXTPA_CONFIG_Cmd_Param_t;
393 
394  /** No response parameters*/
395 
396 #define SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL)
397  /** Command parameters */
398  typedef enum
399  {
400  FLASH_ACTIVITY_CONTROL_PES,
401  FLASH_ACTIVITY_CONTROL_SEM7,
403 
404  /** No response parameters*/
405 
406  /* Exported type --------------------------------------------------------*/
407 
408 typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t;
409 
410 /*
411  * At startup, the informations relative to the wireless binary are stored in RAM trough a structure defined by
412  * SHCI_WirelessFwInfoTable_t.This structure contains 4 fields (Version,MemorySize, Stack_info and a reserved part)
413  * each of those coded on 32 bits as shown on the table below:
414  *
415  *
416  * |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |
417  * -------------------------------------------------------------------------------------------------
418  * Version | Major version | Minor version | Sub version | Branch |Releas Type|
419  * -------------------------------------------------------------------------------------------------
420  * MemorySize | SRAM2B (kB) | SRAM2A (kB) | SRAM1 (kB) | FLASH (4kb) |
421  * -------------------------------------------------------------------------------------------------
422  * Info stack | Reserved | Reserved | Reserved | Type (MAC,Thread,BLE) |
423  * -------------------------------------------------------------------------------------------------
424  * Reserved | Reserved | Reserved | Reserved | Reserved |
425  * -------------------------------------------------------------------------------------------------
426  *
427  */
428 
429 /* Field Version */
430 #define INFO_VERSION_MAJOR_OFFSET 24
431 #define INFO_VERSION_MAJOR_MASK 0xff000000
432 #define INFO_VERSION_MINOR_OFFSET 16
433 #define INFO_VERSION_MINOR_MASK 0x00ff0000
434 #define INFO_VERSION_SUB_OFFSET 8
435 #define INFO_VERSION_SUB_MASK 0x0000ff00
436 #define INFO_VERSION_BRANCH_OFFSET 4
437 #define INFO_VERSION_BRANCH_MASK 0x0000000f0
438 #define INFO_VERSION_TYPE_OFFSET 0
439 #define INFO_VERSION_TYPE_MASK 0x00000000f
440 
441 #define INFO_VERSION_TYPE_RELEASE 1
442 
443 /* Field Memory */
444 #define INFO_SIZE_SRAM2B_OFFSET 24
445 #define INFO_SIZE_SRAM2B_MASK 0xff000000
446 #define INFO_SIZE_SRAM2A_OFFSET 16
447 #define INFO_SIZE_SRAM2A_MASK 0x00ff0000
448 #define INFO_SIZE_SRAM1_OFFSET 8
449 #define INFO_SIZE_SRAM1_MASK 0x0000ff00
450 #define INFO_SIZE_FLASH_OFFSET 0
451 #define INFO_SIZE_FLASH_MASK 0x000000ff
452 
453 /* Field stack information */
454 #define INFO_STACK_TYPE_OFFSET 0
455 #define INFO_STACK_TYPE_MASK 0x000000ff
456 #define INFO_STACK_TYPE_NONE 0
457 
458 #define INFO_STACK_TYPE_BLE_STANDARD 0x01
459 #define INFO_STACK_TYPE_BLE_HCI 0x02
460 #define INFO_STACK_TYPE_BLE_LIGHT 0x03
461 #define INFO_STACK_TYPE_THREAD_FTD 0x10
462 #define INFO_STACK_TYPE_THREAD_MTD 0x11
463 #define INFO_STACK_TYPE_ZIGBEE_FFD 0x30
464 #define INFO_STACK_TYPE_ZIGBEE_RFD 0x31
465 #define INFO_STACK_TYPE_MAC 0x40
466 #define INFO_STACK_TYPE_BLE_THREAD_FTD_STATIC 0x50
467 #define INFO_STACK_TYPE_802154_LLD_TESTS 0x60
468 #define INFO_STACK_TYPE_802154_PHY_VALID 0x61
469 #define INFO_STACK_TYPE_BLE_PHY_VALID 0x62
470 #define INFO_STACK_TYPE_BLE_LLD_TESTS 0x63
471 #define INFO_STACK_TYPE_BLE_RLV 0x64
472 #define INFO_STACK_TYPE_802154_RLV 0x65
473 #define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_STATIC 0x70
474 
475 typedef struct {
476 /**
477  * Wireless Info
478  */
479  uint8_t VersionMajor;
480  uint8_t VersionMinor;
481  uint8_t VersionSub;
482  uint8_t VersionBranch;
483  uint8_t VersionReleaseType;
484  uint8_t MemorySizeSram2B; /*< Multiple of 1K */
485  uint8_t MemorySizeSram2A; /*< Multiple of 1K */
486  uint8_t MemorySizeSram1; /*< Multiple of 1K */
487  uint8_t MemorySizeFlash; /*< Multiple of 4K */
488  uint8_t StackType;
489 /**
490  * Fus Info
491  */
493  uint8_t FusVersionMinor;
494  uint8_t FusVersionSub;
495  uint8_t FusMemorySizeSram2B; /*< Multiple of 1K */
496  uint8_t FusMemorySizeSram2A; /*< Multiple of 1K */
497  uint8_t FusMemorySizeFlash; /*< Multiple of 4K */
499 
500 
501 /* Exported functions ------------------------------------------------------- */
502 
503 /**
504  * For all SHCI_C2_FUS_xxx() command:
505  * When the wireless FW is running on the CPU2, the command returns SHCI_FUS_CMD_NOT_SUPPORTED
506  * When any FUS command is sent after the SHCI_FUS_CMD_NOT_SUPPORTED has been received,
507  * the CPU2 switches on the RSS ( This reboots automatically the device )
508  */
509  /**
510  * SHCI_C2_FUS_GetState
511  * @brief Read the FUS State
512  * If the user is not interested by the Error code response, a null value may
513  * be passed as parameter
514  *
515  * @param p_rsp : return the error code when the FUS State Value = 0xFF
516  * @retval FUS State Values
517  */
519 
520  /**
521  * SHCI_C2_FUS_FwUpgrade
522  * @brief Request the FUS to install the CPU2 firmware update
523  *
524  * @param fw_src_add: Address of the firmware image location
525  * @param fw_dest_add: Address of the firmware destination
526  * @retval Status
527  */
528  SHCI_CmdStatus_t SHCI_C2_FUS_FwUpgrade( uint32_t fw_src_add, uint32_t fw_dest_add );
529 
530  /**
531  * SHCI_C2_FUS_FwDelete
532  * @brief Delete the wireless stack on CPU2
533  *
534  * @param None
535  * @retval Status
536  */
537  SHCI_CmdStatus_t SHCI_C2_FUS_FwDelete( void );
538 
539  /**
540  * SHCI_C2_FUS_UpdateAuthKey
541  * @brief Request the FUS to update the authentication key
542  *
543  * @param pCmdPacket
544  * @retval Status
545  */
546  SHCI_CmdStatus_t SHCI_C2_FUS_UpdateAuthKey( SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t *pParam );
547 
548  /**
549  * SHCI_C2_FUS_LockAuthKey
550  * @brief Request the FUS to prevent any future update of the authentication key
551  *
552  * @param None
553  * @retval Status
554  */
555  SHCI_CmdStatus_t SHCI_C2_FUS_LockAuthKey( void );
556 
557  /**
558  * SHCI_C2_FUS_StoreUsrKey
559  * @brief Request the FUS to store the user key
560  *
561  * @param pParam : command parameter
562  * @param p_key_index : Index allocated by the FUS to the stored key
563  *
564  * @retval Status
565  */
566  SHCI_CmdStatus_t SHCI_C2_FUS_StoreUsrKey( SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t *pParam, uint8_t *p_key_index );
567 
568  /**
569  * SHCI_C2_FUS_LoadUsrKey
570  * @brief Request the FUS to load the user key into the AES
571  *
572  * @param key_index : index of the user key to load in AES1
573  * @retval Status
574  */
575  SHCI_CmdStatus_t SHCI_C2_FUS_LoadUsrKey( uint8_t key_index );
576 
577  /**
578  * SHCI_C2_FUS_StartWs
579  * @brief Request the FUS to reboot on the wireless stack
580  *
581  * @param None
582  * @retval Status
583  */
584  SHCI_CmdStatus_t SHCI_C2_FUS_StartWs( void );
585 
586  /**
587  * SHCI_C2_FUS_LockUsrKey
588  * @brief Request the FUS to lock the user key so that it cannot be updated later on
589  *
590  * @param key_index : index of the user key to lock
591  * @retval Status
592  */
593  SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey( uint8_t key_index );
594 
595  /**
596  * SHCI_C2_BLE_Init
597  * @brief Provides parameters and starts the BLE Stack
598  *
599  * @param pCmdPacket : Parameters to be provided to the BLE Stack
600  * @retval Status
601  */
602  SHCI_CmdStatus_t SHCI_C2_BLE_Init( SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket );
603 
604  /**
605  * SHCI_C2_THREAD_Init
606  * @brief Starts the THREAD Stack
607  *
608  * @param None
609  * @retval Status
610  */
611  SHCI_CmdStatus_t SHCI_C2_THREAD_Init( void );
612 
613  /**
614  * SHCI_C2_LLDTESTS_Init
615  * @brief Starts the LLD tests CLI
616  *
617  * @param param_size : Nb of bytes
618  * @param p_param : pointeur with data to give from M4 to M0
619  * @retval Status
620  */
621  SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init( uint8_t param_size, uint8_t * p_param );
622 
623  /**
624  * SHCI_C2_LLD_BLE_Init
625  * @brief Starts the LLD tests CLI
626  *
627  * @param param_size : Nb of bytes
628  * @param p_param : pointeur with data to give from M4 to M0
629  * @retval Status
630  */
631  SHCI_CmdStatus_t SHCI_C2_LLD_BLE_Init( uint8_t param_size, uint8_t * p_param );
632 
633  /**
634  * SHCI_C2_ZIGBEE_Init
635  * @brief Starts the Zigbee Stack
636  *
637  * @param None
638  * @retval Status
639  */
640  SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init( void );
641 
642  /**
643  * SHCI_C2_DEBUG_Init
644  * @brief Starts the Traces
645  *
646  * @param None
647  * @retval Status
648  */
649  SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket );
650 
651  /**
652  * SHCI_C2_FLASH_EraseActivity
653  * @brief Provides the information of the start and the end of a flash erase window on the CPU1
654  *
655  * @param erase_activity: Start/End of erase activity
656  * @retval Status
657  */
658  SHCI_CmdStatus_t SHCI_C2_FLASH_EraseActivity( SHCI_EraseActivity_t erase_activity );
659 
660  /**
661  * SHCI_C2_CONCURRENT_SetMode
662  * @brief Enable/Disable Thread on CPU2 (M0+)
663  *
664  * @param Mode: BLE or Thread enable flag
665  * @retval Status
666  */
667  SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode( SHCI_C2_CONCURRENT_Mode_Param_t Mode );
668 
669  /**
670  * SHCI_C2_FLASH_StoreData
671  * @brief Store Data in Flash
672  *
673  * @param Ip: BLE or THREAD
674  * @retval Status
675  */
676  SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData( SHCI_C2_FLASH_Ip_t Ip );
677 
678  /**
679  * SHCI_C2_FLASH_EraseData
680  * @brief Erase Data in Flash
681  *
682  * @param Ip: BLE or THREAD
683  * @retval Status
684  */
685  SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData( SHCI_C2_FLASH_Ip_t Ip );
686 
687  /**
688  * SHCI_C2_RADIO_AllowLowPower
689  * @brief Allow or forbid IP_radio (802_15_4 or BLE) to enter in low power mode.
690  *
691  * @param Ip: BLE or 802_15_5
692  * @param FlagRadioLowPowerOn: True or false
693  * @retval Status
694  */
695  SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower( SHCI_C2_FLASH_Ip_t Ip,uint8_t FlagRadioLowPowerOn);
696 
697 
698  /**
699  * SHCI_C2_MAC_802_15_4_Init
700  * @brief Starts the MAC 802.15.4 on M0
701  *
702  * @param None
703  * @retval Status
704  */
705  SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init( void );
706 
707  /**
708  * SHCI_GetWirelessFwInfo
709  * @brief This function read back the informations relative to the wireless binary loaded.
710  * Refer yourself to SHCI_WirelessFwInfoTable_t structure to get the significance
711  * of the different parameters returned.
712  * @param pWirelessInfo : Pointer to WirelessFwInfo_t.
713  *
714  * @retval SHCI_Success
715  */
716  SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo );
717 
718  /**
719  * SHCI_C2_Reinit
720  * @brief This is required to allow the CPU1 to fake a set C2BOOT when it has already been set.
721  * In order to fake a C2BOOT, the CPU1 shall :
722  * - Send SHCI_C2_Reinit()
723  * - call SEV instruction
724  * WARNING:
725  * This function is intended to be used by the SBSFU
726  *
727  * @param None
728  * @retval Status
729  */
730  SHCI_CmdStatus_t SHCI_C2_Reinit( void );
731 
732  /**
733  * SHCI_C2_ExtpaConfig
734  * @brief Send the Ext PA configuration
735  * When the CPU2 receives the command, it controls the Ext PA as requested by the configuration
736  * This configures only which IO is used to enable/disable the ExtPA and the associated polarity
737  * This command has no effect on the other IO that is used to control the mode of the Ext PA (Rx/Tx)
738  *
739  * @param gpio_port: GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WBxx family
740  * @param gpio_pin_number: This parameter can be one of GPIO_PIN_x (= LL_GPIO_PIN_x) where x can be (0..15).
741  * @param gpio_polarity: This parameter can be either
742  * - EXT_PA_ENABLED_LOW: ExtPA is enabled when GPIO is low
743  * - EXT_PA_ENABLED_HIGH: ExtPA is enabled when GPIO is high
744  * @param gpio_status: This parameter can be either
745  * - EXT_PA_DISABLED: Stop driving the ExtPA
746  * - EXT_PA_ENABLED: Drive the ExtPA according to radio activity
747  * (ON before the Event and OFF at the end of the event)
748  * @retval Status
749  */
750  SHCI_CmdStatus_t SHCI_C2_ExtpaConfig(uint32_t gpio_port, uint16_t gpio_pin_number, uint8_t gpio_polarity, uint8_t gpio_status);
751 
752  /**
753  * SHCI_C2_SetFlashActivityControl
754  * @brief Set the mechanism to be used on CPU2 to prevent the CPU1 to either write or erase in flash
755  *
756  * @param Source: It can be one of the following list
757  * - FLASH_ACTIVITY_CONTROL_PES : The CPU2 set the PES bit to prevent the CPU1 to either read or write in flash
758  * - FLASH_ACTIVITY_CONTROL_SEM7 : The CPU2 gets the semaphore 7 to prevent the CPU1 to either read or write in flash.
759  * This requires the CPU1 to first get semaphore 7 before erasing or writing the flash.
760  *
761  * @retval Status
762  */
763  SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl(SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source);
764 
765  #ifdef __cplusplus
766 }
767 #endif
768 
769 #endif /*__SHCI_H */
770 
771 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
uint8_t VersionMajor
Wireless Info.
Definition: shci.h:479
SHCI_C2_Ble_Init_Cmd_Param_t Param
Does not need to be initialized by the user.
Definition: shci.h:290
SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower(SHCI_C2_FLASH_Ip_t Ip, uint8_t FlagRadioLowPowerOn)
SHCI_C2_RADIO_AllowLowPower.
SHCI_CmdStatus_t SHCI_C2_DEBUG_Init(SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket)
SHCI_C2_DEBUG_Init.
SHCI_CmdStatus_t SHCI_C2_BLE_Init(SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket)
SHCI_C2_BLE_Init.
SHCI_OCF_t
THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU2 DEFINITION.
Definition: shci.h:104
SHCI_CmdStatus_t SHCI_C2_FUS_LoadUsrKey(uint8_t key_index)
SHCI_C2_FUS_LoadUsrKey.
uint32_t BleBufferSize
Size of the Buffer allocated in pBleBufferAddress.
Definition: shci.h:269
SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl(SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source)
SHCI_C2_SetFlashActivityControl.
uint8_t SHCI_C2_FUS_GetState(SHCI_FUS_GetState_ErrorCode_t *p_rsp)
For all SHCI_C2_FUS_xxx() command: When the wireless FW is running on the CPU2, the command returns S...
SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init(uint8_t param_size, uint8_t *p_param)
SHCI_C2_LLDTESTS_Init.
SHCI_CmdStatus_t SHCI_C2_ExtpaConfig(uint32_t gpio_port, uint16_t gpio_pin_number, uint8_t gpio_polarity, uint8_t gpio_status)
SHCI_C2_ExtpaConfig.
SHCI_CmdStatus_t SHCI_C2_THREAD_Init(void)
SHCI_C2_THREAD_Init.
SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData(SHCI_C2_FLASH_Ip_t Ip)
SHCI_C2_FLASH_StoreData.
SHCI_C2_CONCURRENT_Mode_Param_t
command parameters
Definition: shci.h:342
SHCI_CmdStatus_t SHCI_C2_FUS_StoreUsrKey(SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t *pParam, uint8_t *p_key_index)
SHCI_C2_FUS_StoreUsrKey.
SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init(void)
SHCI_C2_MAC_802_15_4_Init.
SHCI_CmdStatus_t SHCI_C2_FUS_FwDelete(void)
SHCI_C2_FUS_FwDelete.
SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t
Command parameters.
Definition: shci.h:398
SHCI_CmdStatus_t SHCI_C2_FUS_StartWs(void)
SHCI_C2_FUS_StartWs.
uint8_t FusVersionMajor
Fus Info.
Definition: shci.h:492
SHCI_C2_FLASH_Ip_t
command parameters
Definition: shci.h:353
MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t
No response parameters.
Definition: shci.h:408
SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData(SHCI_C2_FLASH_Ip_t Ip)
SHCI_C2_FLASH_EraseData.
Mailbox definition.
SHCI_CmdStatus_t SHCI_GetWirelessFwInfo(WirelessFwInfo_t *pWirelessInfo)
SHCI_GetWirelessFwInfo.
SHCI_CmdStatus_t SHCI_C2_FUS_FwUpgrade(uint32_t fw_src_add, uint32_t fw_dest_add)
SHCI_C2_FUS_FwUpgrade.
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode(SHCI_C2_CONCURRENT_Mode_Param_t Mode)
SHCI_C2_CONCURRENT_SetMode.
typedef PACKED_STRUCT
THE ORDER SHALL NOT BE CHANGED.
Definition: shci.h:68
SHCI_CmdStatus_t SHCI_C2_LLD_BLE_Init(uint8_t param_size, uint8_t *p_param)
SHCI_C2_LLD_BLE_Init.
SHCI_EraseActivity_t
Command parameters.
Definition: shci.h:332
SHCI_FUS_GetState_ErrorCode_t
No command parameters.
Definition: shci.h:148
SHCI_CmdStatus_t SHCI_C2_Reinit(void)
SHCI_C2_Reinit.
SHCI_CmdStatus_t SHCI_C2_FUS_LockAuthKey(void)
SHCI_C2_FUS_LockAuthKey.
SHCI_CmdStatus_t SHCI_C2_FUS_UpdateAuthKey(SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t *pParam)
SHCI_C2_FUS_UpdateAuthKey.
SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init(void)
SHCI_C2_ZIGBEE_Init.
SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey(uint8_t key_index)
SHCI_C2_FUS_LockUsrKey.
SHCI_SUB_EVT_CODE_t
THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU1 DEFINITION.
Definition: shci.h:62
SHCI_CmdStatus_t SHCI_C2_FLASH_EraseActivity(SHCI_EraseActivity_t erase_activity)
SHCI_C2_FLASH_EraseActivity.
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