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nuc472_eth.h
1 /*
2  * Copyright (c) 2018 Nuvoton Technology Corp.
3  * Copyright (c) 2018 ARM Limited
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  * Description: NUC472 EMAC driver header file
18  */
19 #include "NUC472_442.h"
20 #include "numaker_emac_config.h"
21 #ifndef _NUC472_ETH_
22 #define _NUC472_ETH_
23 
24 /* Generic MII registers. */
25 
26 #define MII_BMCR 0x00 /* Basic mode control register */
27 #define MII_BMSR 0x01 /* Basic mode status register */
28 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
29 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
30 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
31 #define MII_LPA 0x05 /* Link partner ability reg */
32 #define MII_EXPANSION 0x06 /* Expansion register */
33 #define MII_DCOUNTER 0x12 /* Disconnect counter */
34 #define MII_FCSCOUNTER 0x13 /* False carrier counter */
35 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
36 #define MII_RERRCOUNTER 0x15 /* Receive error counter */
37 #define MII_SREVISION 0x16 /* Silicon revision */
38 #define MII_RESV1 0x17 /* Reserved... */
39 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
40 #define MII_PHYADDR 0x19 /* PHY address */
41 #define MII_RESV2 0x1a /* Reserved... */
42 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
43 #define MII_NCONFIG 0x1c /* Network interface config */
44 
45 /* Basic mode control register. */
46 #define BMCR_RESV 0x007f /* Unused... */
47 #define BMCR_CTST 0x0080 /* Collision test */
48 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
49 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
50 #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
51 #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
52 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
53 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
54 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
55 #define BMCR_RESET 0x8000 /* Reset the DP83840 */
56 
57 /* Basic mode status register. */
58 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
59 #define BMSR_JCD 0x0002 /* Jabber detected */
60 #define BMSR_LSTATUS 0x0004 /* Link status */
61 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
62 #define BMSR_RFAULT 0x0010 /* Remote fault detected */
63 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
64 #define BMSR_RESV 0x07c0 /* Unused... */
65 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
66 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
67 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
68 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
69 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
70 
71 /* Advertisement control register. */
72 #define ADVERTISE_SLCT 0x001f /* Selector bits */
73 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
74 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
75 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
76 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
77 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
78 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
79 #define ADVERTISE_RESV 0x1c00 /* Unused... */
80 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
81 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
82 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
83 
84 #define RX_DESCRIPTOR_NUM NU_RX_RING_LEN//4 //2 // 4: Max Number of Rx Frame Descriptors
85 #define TX_DESCRIPTOR_NUM NU_TX_RING_LEN//4 //2 // 4: Max number of Tx Frame Descriptors
86 
87 #define PACKET_BUFFER_SIZE ( NU_ETH_MAX_FLEN + ((NU_ETH_MAX_FLEN%4) ? (4 - (NU_ETH_MAX_FLEN%4)) : 0) ) //For DMA 4 bytes alignment
88 
89 #define CONFIG_PHY_ADDR 1
90 
91 
92 // Frame Descriptor's Owner bit
93 #define OWNERSHIP_EMAC 0x80000000 // 1 = EMAC
94 //#define OWNERSHIP_CPU 0x7fffffff // 0 = CPU
95 
96 
97 
98 // Rx Frame Descriptor Status
99 #define RXFD_RXGD 0x00100000 // Receiving Good Packet Received
100 #define RXFD_RTSAS 0x00800000 // RX Time Stamp Available
101 
102 
103 // Tx Frame Descriptor's Control bits
104 #define TXFD_TTSEN 0x08 // Tx Time Stamp Enable
105 #define TXFD_INTEN 0x04 // Interrupt Enable
106 #define TXFD_CRCAPP 0x02 // Append CRC
107 #define TXFD_PADEN 0x01 // Padding Enable
108 
109 // Tx Frame Descriptor Status
110 #define TXFD_TXCP 0x00080000 // Transmission Completion
111 #define TXFD_TTSAS 0x08000000 // TX Time Stamp Available
112 
113 // Tx/Rx buffer descriptor structure
114 struct eth_descriptor;
115 struct eth_descriptor {
116  uint32_t status1;
117  uint8_t *buf;
118  uint32_t status2;
119  struct eth_descriptor *next;
120 #ifdef TIME_STAMPING
121  uint32_t backup1;
122  uint32_t backup2;
123  uint32_t reserved1;
124  uint32_t reserved2;
125 #endif
126 };
127 
128 #ifdef TIME_STAMPING
129 
130 #define ETH_TS_ENABLE() do{EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;}while(0)
131 #define ETH_TS_START() do{EMAC->TSCTL |= (EMAC_TSCTL_TSMODE_Msk | EMAC_TSCTL_TSIEN_Msk);}while(0)
132 s32_t ETH_settime(u32_t sec, u32_t nsec);
133 s32_t ETH_gettime(u32_t *sec, u32_t *nsec);
134 s32_t ETH_updatetime(u32_t neg, u32_t sec, u32_t nsec);
135 s32_t ETH_adjtimex(int ppm);
136 void ETH_setinc(void);
137 
138 #endif
139 
140 #endif /* _NUC472_ETH_ */
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