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MX25LM51245G_config.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2018 ARM Limited
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 #ifndef MBED_QSPI_FLASH_MX25LM51245G_H
18 #define MBED_QSPI_FLASH_MX25LM51245G_H
19 
20 
21 #define QSPI_FLASH_CHIP_STRING "macronix MX25LM51245G"
22 
23 // Command for reading status register
24 #define QSPI_CMD_RDSR 0x05
25 // Command for reading configuration register
26 #define QSPI_CMD_RDCR0 0x15
27 #define QSPI_CMD_RDCR1 0x71
28 // Command for writing status/configuration register
29 #define QSPI_CMD_WRSR 0x01
30 // Command for reading security register
31 #define QSPI_CMD_RDSCUR 0x2B
32 
33 // Command for setting Reset Enable
34 #define QSPI_CMD_RSTEN 0x66
35 // Command for setting Reset
36 #define QSPI_CMD_RST 0x99
37 
38 // Command for setting write enable
39 #define QSPI_CMD_WREN 0x06
40 // Command for setting write disable
41 #define QSPI_CMD_WRDI 0x04
42 
43 // WRSR operations max time [us] (datasheet max time + 15%)
44 #define QSPI_WRSR_MAX_TIME 34500 // 30ms
45 // general wait max time [us]
46 #define QSPI_WAIT_MAX_TIME 100000 // 100ms
47 
48 
49 // Commands for writing (page programming)
50 // Only single/octal mode supported with this memory
51 // So only single 1-1-1 mode in this QSPI config
52 #define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
53 // write operations max time [us] (datasheet max time + 15%)
54 #define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
55 
56 #define QSPI_PAGE_SIZE 256 // 256B
57 #define QSPI_SECTOR_SIZE 4096 // 4kB
58 #define QSPI_SECTOR_COUNT 131072 // 512MB / QSPI_SECTOR_SIZE
59 
60 // Commands for reading
61 // Only single/octal mode supported with this memory
62 // So only single 1-1-1 mode in this QSPI config
63 #define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
64 #define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
65 
66 #define QSPI_READ_1IO_DUMMY_CYCLE 0
67 #define QSPI_READ_FAST_DUMMY_CYCLE 8
68 
69 // Commands for erasing
70 #define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
71 //#define QSPI_CMD_ERASE_BLOCK_32 // not supported
72 #define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
73 #define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
74 
75 // erase operations max time [us] (datasheet max time + 15%)
76 #define QSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
77 #define QSPI_ERASE_BLOCK_64_MAX_TIME 2400000 // 2s
78 
79 // max frequency for basic rw operation (for fast mode)
80 #define QSPI_COMMON_MAX_FREQUENCY 66000000
81 
82 #define QSPI_STATUS_REG_SIZE 1
83 #define QSPI_CONFIG_REG_0_SIZE 1
84 #define QSPI_CONFIG_REG_1_SIZE 12
85 #define QSPI_SECURITY_REG_SIZE 1
86 #define QSPI_MAX_REG_SIZE 12
87 
88 // status register
89 #define STATUS_BIT_WIP (1 << 0) // write in progress bit
90 #define STATUS_BIT_WEL (1 << 1) // write enable latch
91 #define STATUS_BIT_BP0 (1 << 2) //
92 #define STATUS_BIT_BP1 (1 << 3) //
93 #define STATUS_BIT_BP2 (1 << 4) //
94 #define STATUS_BIT_BP3 (1 << 5) //
95 
96 #endif // MBED_QSPI_FLASH_MX25LM51245G_H
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