LSM303C_ACC_driver.h

00001 /**
00002  ******************************************************************************
00003  * @file    LSM303C_ACC_driver.h
00004  * @author  MEMS Application Team
00005  * @version V1.1
00006  * @date    24-February-2016
00007  * @brief   LSM303C Accelerometer header driver file
00008  ******************************************************************************
00009  * @attention
00010  *
00011  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012  *
00013  * Redistribution and use in source and binary forms, with or without modification,
00014  * are permitted provided that the following conditions are met:
00015  *   1. Redistributions of source code must retain the above copyright notice,
00016  *      this list of conditions and the following disclaimer.
00017  *   2. Redistributions in binary form must reproduce the above copyright notice,
00018  *      this list of conditions and the following disclaimer in the documentation
00019  *      and/or other materials provided with the distribution.
00020  *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021  *      may be used to endorse or promote products derived from this software
00022  *      without specific prior written permission.
00023  *
00024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034  *
00035  ******************************************************************************
00036  */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __LSM303C_ACC_DRIVER__H
00040 #define __LSM303C_ACC_DRIVER__H
00041 
00042 /* Includes ------------------------------------------------------------------*/
00043 #include <stdint.h>
00044 
00045 /* Exported types ------------------------------------------------------------*/
00046 
00047 #ifdef __cplusplus
00048 extern "C" {
00049 #endif
00050 
00051 //these could change accordingly with the architecture
00052 
00053 #ifndef __ARCHDEP__TYPES
00054 #define __ARCHDEP__TYPES
00055 
00056 typedef unsigned char u8_t;
00057 typedef unsigned short int u16_t;
00058 typedef unsigned int u32_t;
00059 typedef int i32_t;
00060 typedef short int i16_t;
00061 typedef signed char i8_t;
00062 
00063 #endif /*__ARCHDEP__TYPES*/
00064 
00065 /* Exported common structure --------------------------------------------------------*/
00066 
00067 #ifndef __SHARED__TYPES
00068 #define __SHARED__TYPES
00069 
00070 typedef union{
00071     i16_t i16bit[3];
00072     u8_t u8bit[6];
00073 } Type3Axis16bit_U; 
00074 
00075 typedef union{
00076     i16_t i16bit;
00077     u8_t u8bit[2];
00078 } Type1Axis16bit_U;
00079 
00080 typedef union{
00081     i32_t i32bit;
00082     u8_t u8bit[4];
00083 } Type1Axis32bit_U;
00084 
00085 typedef enum {
00086   MEMS_SUCCESS = 0x01,
00087   MEMS_ERROR   = 0x00   
00088 } status_t;
00089 
00090 #endif /*__SHARED__TYPES*/
00091 
00092 /* Exported macro ------------------------------------------------------------*/
00093 
00094 /* Exported constants --------------------------------------------------------*/
00095 
00096 /************** I2C Address *****************/
00097 
00098 #define LSM303C_ACC_I2C_ADDRESS           0x3A
00099 #define I_AM_LSM303C_ACC                  0x41
00100 
00101 /* Acceleration Registers */
00102 #define LSM303C_WHO_AM_I_REG_A            0x0F  /* device identification register */
00103 #define LSM303C_ACT_THS_A                 0x1E
00104 #define LSM303C_ACT_DUR_A                 0x1F
00105 #define LSM303C_CTRL_REG1_A               0x20  /* Control register 1 acceleration */
00106 #define LSM303C_CTRL_REG2_A               0x21  /* Control register 2 acceleration */
00107 #define LSM303C_CTRL_REG3_A               0x22  /* Control register 3 acceleration */
00108 #define LSM303C_CTRL_REG4_A               0x23  /* Control register 4 acceleration */
00109 #define LSM303C_CTRL_REG5_A               0x24  /* Control register 5 acceleration */
00110 #define LSM303C_CTRL_REG6_A               0x25  /* Control register 6 acceleration */
00111 #define LSM303C_CTRL_REG7_A               0x26  /* Control register 6 acceleration */   
00112 #define LSM303C_STATUS_REG_A              0x27  /* Status register acceleration */
00113 #define LSM303C_OUT_X_L_A                 0x28  /* Output Register X acceleration */
00114 #define LSM303C_OUT_X_H_A                 0x29  /* Output Register X acceleration */
00115 #define LSM303C_OUT_Y_L_A                 0x2A  /* Output Register Y acceleration */
00116 #define LSM303C_OUT_Y_H_A                 0x2B  /* Output Register Y acceleration */
00117 #define LSM303C_OUT_Z_L_A                 0x2C  /* Output Register Z acceleration */
00118 #define LSM303C_OUT_Z_H_A                 0x2D  /* Output Register Z acceleration */ 
00119 #define LSM303C_FIFO_CTRL                 0x2E  /* Fifo control Register acceleration */
00120 #define LSM303C_FIFO_SRC                  0x2F  /* Fifo src Register acceleration */
00121 
00122 #define LSM303C_IG_CFG1_A                 0x30  /* Interrupt 1 configuration Register acceleration */
00123 #define LSM303C_IG_SRC1_A                 0x31  /* Interrupt 1 source Register acceleration */
00124 #define LSM303C_IG_THS_X1_A               0x32
00125 #define LSM303C_IG_THS_Y1_A               0x33
00126 #define LSM303C_IG_THS_Z1_A               0x34
00127    
00128 #define LSM303C_IG_DUR1_A                 0x32
00129 #define LSM303C_INT1_DURATION_A           0x33  /* Interrupt 1 DURATION register acceleration */
00130 
00131 #define LSM303C_INT2_CFG_A                0x34  /* Interrupt 2 configuration Register acceleration */
00132 #define LSM303C_INT2_SOURCE_A             0x35  /* Interrupt 2 source Register acceleration */
00133 #define LSM303C_INT2_THS_A                0x36  /* Interrupt 2 Threshold register acceleration */
00134 #define LSM303C_INT2_DURATION_A           0x37  /* Interrupt 2 DURATION register acceleration */
00135 
00136 #define LSM303C_CLICK_CFG_A               0x38  /* Click configuration Register acceleration */
00137 #define LSM303C_CLICK_SOURCE_A            0x39  /* Click 2 source Register acceleration */
00138 #define LSM303C_CLICK_THS_A               0x3A  /* Click 2 Threshold register acceleration */
00139 
00140 #define LSM303C_TIME_LIMIT_A              0x3B  /* Time Limit Register acceleration */
00141 #define LSM303C_TIME_LATENCY_A            0x3C  /* Time Latency Register acceleration */
00142 #define LSM303C_TIME_WINDOW_A             0x3D  /* Time window register acceleration */
00143 
00144 /* Private Function Prototype -------------------------------------------------------*/
00145 
00146 void LSM303C_ACC_SwapHighLowByte(u8_t *bufferToSwap, u8_t numberOfByte, u8_t dimension);
00147 
00148 /* Public Function Prototypes ------------------------------------------------*/
00149 
00150 status_t LSM303C_ACC_ReadReg( void *handle, u8_t Reg, u8_t* Data );
00151 status_t LSM303C_ACC_WriteReg( void *handle, u8_t Reg, u8_t Data ); 
00152 
00153 
00154 /*******************************************************************************
00155 * Register      : WHO_AM_I
00156 * Address       : 0X0F
00157 * Bit Group Name: WHO_AM_I
00158 * Permission    : RO
00159 *******************************************************************************/
00160 #define     LSM303C_ACC_WHO_AM_I_MASK     0xFF
00161 #define     LSM303C_ACC_WHO_AM_I_POSITION     0
00162 status_t LSM303C_ACC_R_WHO_AM_I(void *handle, u8_t *value);
00163 
00164 /*******************************************************************************
00165 * Register      : CTRL_REG1
00166 * Address       : 0X20
00167 * Bit Group Name: XEN
00168 * Permission    : RW
00169 *******************************************************************************/
00170 typedef enum {
00171     LSM303C_ACC_XEN_DISABLED       =0x00,
00172     LSM303C_ACC_XEN_ENABLED        =0x01,
00173 } LSM303C_ACC_XEN_t;
00174 
00175 #define     LSM303C_ACC_XEN_MASK      0x01
00176 status_t  LSM303C_ACC_W_XEN(void *handle, LSM303C_ACC_XEN_t newValue);
00177 status_t LSM303C_ACC_R_XEN(void *handle, LSM303C_ACC_XEN_t *value);
00178 
00179 /*******************************************************************************
00180 * Register      : CTRL_REG1
00181 * Address       : 0X20
00182 * Bit Group Name: YEN
00183 * Permission    : RW
00184 *******************************************************************************/
00185 typedef enum {
00186     LSM303C_ACC_YEN_DISABLED       =0x00,
00187     LSM303C_ACC_YEN_ENABLED        =0x02,
00188 } LSM303C_ACC_YEN_t;
00189 
00190 #define     LSM303C_ACC_YEN_MASK      0x02
00191 status_t  LSM303C_ACC_W_YEN(void *handle, LSM303C_ACC_YEN_t newValue);
00192 status_t LSM303C_ACC_R_YEN(void *handle, LSM303C_ACC_YEN_t *value);
00193 
00194 /*******************************************************************************
00195 * Register      : CTRL_REG1
00196 * Address       : 0X20
00197 * Bit Group Name: ZEN
00198 * Permission    : RW
00199 *******************************************************************************/
00200 typedef enum {
00201     LSM303C_ACC_ZEN_DISABLED       =0x00,
00202     LSM303C_ACC_ZEN_ENABLED        =0x04,
00203 } LSM303C_ACC_ZEN_t;
00204 
00205 #define     LSM303C_ACC_ZEN_MASK      0x04
00206 status_t  LSM303C_ACC_W_ZEN(void *handle, LSM303C_ACC_ZEN_t newValue);
00207 status_t LSM303C_ACC_R_ZEN(void *handle, LSM303C_ACC_ZEN_t *value);
00208 
00209 /*******************************************************************************
00210 * Register      : CTRL_REG1
00211 * Address       : 0X20
00212 * Bit Group Name: ODR
00213 * Permission    : RW
00214 *******************************************************************************/
00215 typedef enum {
00216     LSM303C_ACC_ODR_DO_PWR_DOWN     =0x00,
00217     LSM303C_ACC_ODR_DO_10Hz         =0x10,
00218     LSM303C_ACC_ODR_DO_50Hz         =0x20,
00219     LSM303C_ACC_ODR_DO_100Hz        =0x30,
00220     LSM303C_ACC_ODR_DO_200Hz        =0x40,
00221     LSM303C_ACC_ODR_DO_400Hz        =0x50,
00222     LSM303C_ACC_ODR_DO_800Hz        =0x60,
00223 } LSM303C_ACC_ODR_t;
00224 
00225 #define     LSM303C_ACC_ODR_MASK      0x70
00226 status_t  LSM303C_ACC_W_ODR(void *handle, LSM303C_ACC_ODR_t newValue);
00227 status_t LSM303C_ACC_R_ODR(void *handle, LSM303C_ACC_ODR_t *value);
00228 
00229 /*******************************************************************************
00230 * Register      : CTRL_REG2
00231 * Address       : 0X21
00232 * Bit Group Name: HPIS1
00233 * Permission    : RW
00234 *******************************************************************************/
00235 typedef enum {
00236     LSM303C_ACC_HPIS1_DISABLED         =0x00,
00237     LSM303C_ACC_HPIS1_ENABLED          =0x01,
00238 } LSM303C_ACC_HPIS1_t;
00239 
00240 #define     LSM303C_ACC_HPIS1_MASK    0x01
00241 status_t  LSM303C_ACC_W_hpf_aoi_en_int1(void *handle, LSM303C_ACC_HPIS1_t newValue);
00242 status_t LSM303C_ACC_R_hpf_aoi_en_int1(void *handle, LSM303C_ACC_HPIS1_t *value);
00243 
00244 /*******************************************************************************
00245 * Register      : CTRL_REG2
00246 * Address       : 0X21
00247 * Bit Group Name: HPIS2
00248 * Permission    : RW
00249 *******************************************************************************/
00250 typedef enum {
00251     LSM303C_ACC_HPIS2_DISABLED         =0x00,
00252     LSM303C_ACC_HPIS2_ENABLED          =0x02,
00253 } LSM303C_ACC_HPIS2_t;
00254 
00255 #define     LSM303C_ACC_HPIS2_MASK    0x02
00256 status_t  LSM303C_ACC_W_hpf_aoi_en_int2(void *handle, LSM303C_ACC_HPIS2_t newValue);
00257 status_t LSM303C_ACC_R_hpf_aoi_en_int2(void *handle, LSM303C_ACC_HPIS2_t *value);
00258 
00259 /*******************************************************************************
00260 * Register      : CTRL_REG2
00261 * Address       : 0X21
00262 * Bit Group Name: FDS
00263 * Permission    : RW
00264 *******************************************************************************/
00265 typedef enum {
00266     LSM303C_ACC_FDS_BYPASSED       =0x00,
00267     LSM303C_ACC_FDS_ENABLED        =0x04,
00268 } LSM303C_ACC_FDS_t;
00269 
00270 #define     LSM303C_ACC_FDS_MASK      0x04
00271 status_t  LSM303C_ACC_W_Data_Filter(void *handle, LSM303C_ACC_FDS_t newValue);
00272 status_t LSM303C_ACC_R_Data_Filter(void *handle, LSM303C_ACC_FDS_t *value);
00273 
00274 /*******************************************************************************
00275 * Register      : CTRL_REG2
00276 * Address       : 0X21
00277 * Bit Group Name: DFC
00278 * Permission    : RW
00279 *******************************************************************************/
00280 typedef enum {
00281     LSM303C_ACC_DFC_50      =0x00,
00282     LSM303C_ACC_DFC_100     =0x20,
00283     LSM303C_ACC_DFC_9       =0x40,
00284     LSM303C_ACC_DFC_400     =0x60,
00285 } LSM303C_ACC_DFC_t;
00286 
00287 #define     LSM303C_ACC_DFC_MASK     0x60
00288 status_t  LSM303C_ACC_W_hpf_cutoff_freq(void *handle, LSM303C_ACC_DFC_t newValue);
00289 status_t LSM303C_ACC_R_hpf_cutoff_freq(void *handle, LSM303C_ACC_DFC_t *value);
00290 
00291 /*******************************************************************************
00292 * Register      : CTRL_REG2
00293 * Address       : 0X21
00294 * Bit Group Name: HPM
00295 * Permission    : RW
00296 *******************************************************************************/
00297 typedef enum {
00298     LSM303C_ACC_HPM_NORMAL              =0x00,
00299     LSM303C_ACC_HPM_REFERENCE_SIGNAL    =0x08,
00300 } LSM303C_ACC_HPM_t;
00301 
00302 #define     LSM303C_ACC_HPM_MASK      0x18
00303 status_t  LSM303C_ACC_W_hpf_mode(void *handle, LSM303C_ACC_HPM_t newValue);
00304 status_t LSM303C_ACC_R_hpf_mode(void *handle, LSM303C_ACC_HPM_t *value);
00305 
00306 /*******************************************************************************
00307 * Register      : CTRL_REG1
00308 * Address       : 0X23
00309 * Bit Group Name: HR
00310 * Permission    : RW
00311 *******************************************************************************/
00312 typedef enum {
00313     LSM303C_ACC_HR_DISABLED        =0x00,
00314     LSM303C_ACC_HR_ENABLED         =0x80,
00315 } LSM303C_ACC_HR_t;
00316 
00317 #define     LSM303C_ACC_HR_MASK   0x80
00318 status_t  LSM303C_ACC_W_HiRes(void *handle, LSM303C_ACC_HR_t newValue);
00319 status_t LSM303C_ACC_R_HiRes(void *handle, LSM303C_ACC_HR_t *value);
00320 
00321 /*******************************************************************************
00322 * Register      : CTRL_REG4
00323 * Address       : 0X23
00324 * Bit Group Name: FS
00325 * Permission    : RW
00326 *******************************************************************************/
00327 typedef enum {
00328     LSM303C_ACC_FS_2G          =0x00,
00329     LSM303C_ACC_FS_4G          =0x20,
00330     LSM303C_ACC_FS_8G          =0x30,
00331 } LSM303C_ACC_FS_t;
00332 
00333 #define     LSM303C_ACC_FS_MASK   0x30
00334 status_t  LSM303C_ACC_W_FullScale(void *handle, LSM303C_ACC_FS_t newValue);
00335 status_t LSM303C_ACC_R_FullScale(void *handle, LSM303C_ACC_FS_t *value);
00336 
00337 /*******************************************************************************
00338 * Register      : CTRL_REG1
00339 * Address       : 0X23
00340 * Bit Group Name: BDU
00341 * Permission    : RW
00342 *******************************************************************************/
00343 typedef enum {
00344     LSM303C_ACC_BDU_DISABLED       =0x00,
00345     LSM303C_ACC_BDU_ENABLED        =0x08,
00346 } LSM303C_ACC_BDU_t;
00347 
00348 #define     LSM303C_ACC_BDU_MASK      0x08
00349 status_t  LSM303C_ACC_W_BlockDataUpdate(void *handle, LSM303C_ACC_BDU_t newValue);
00350 status_t LSM303C_ACC_R_BlockDataUpdate(void *handle, LSM303C_ACC_BDU_t *value);
00351 
00352 /*******************************************************************************
00353 * Register      : CTRL_REG3
00354 * Address       : 0X24
00355 * Bit Group Name: FIFO_EN
00356 * Permission    : RW
00357 *******************************************************************************/
00358 typedef enum {
00359     LSM303C_ACC_FIFO_EN_DISABLED       =0x00,
00360     LSM303C_ACC_FIFO_EN_ENABLED        =0x80,
00361 } LSM303C_ACC_FIFO_EN_t;
00362 
00363 #define     LSM303C_ACC_FIFO_EN_MASK      0x80
00364 status_t  LSM303C_ACC_W_FIFO_EN(void *handle, LSM303C_ACC_FIFO_EN_t newValue);
00365 status_t LSM303C_ACC_R_FIFO_EN(void *handle, LSM303C_ACC_FIFO_EN_t *value);
00366 
00367 
00368 /*******************************************************************************
00369 * Register      : CTRL_REG5
00370 * Address       : 0X25
00371 * Bit Group Name: H_LACTIVE
00372 * Permission    : RW
00373 *******************************************************************************/
00374 typedef enum {
00375     LSM303C_ACC_H_LACTIVE_ACTIVE_HI        =0x00,
00376     LSM303C_ACC_H_LACTIVE_ACTIVE_LO        =0x02,
00377 } LSM303C_ACC_H_LACTIVE_t;
00378 
00379 #define     LSM303C_ACC_H_LACTIVE_MASK    0x02
00380 status_t  LSM303C_ACC_W_IntActive(void *handle, LSM303C_ACC_H_LACTIVE_t newValue);
00381 status_t LSM303C_ACC_R_IntActive(void *handle, LSM303C_ACC_H_LACTIVE_t *value);
00382 
00383 /*******************************************************************************
00384 * Register      : STATUS_REG2
00385 * Address       : 0X27
00386 * Bit Group Name: XDA
00387 * Permission    : RO
00388 *******************************************************************************/
00389 typedef enum {
00390     LSM303C_ACC_XDA_NOT_AVAILABLE          =0x00,
00391     LSM303C_ACC_XDA_AVAILABLE          =0x01,
00392 } LSM303C_ACC_XDA_t;
00393 
00394 #define     LSM303C_ACC_XDA_MASK      0x01
00395 status_t LSM303C_ACC_R_XDataAvail(void *handle, LSM303C_ACC_XDA_t *value);
00396 
00397 /*******************************************************************************
00398 * Register      : STATUS_REG2
00399 * Address       : 0X27
00400 * Bit Group Name: YDA
00401 * Permission    : RO
00402 *******************************************************************************/
00403 typedef enum {
00404     LSM303C_ACC_YDA_NOT_AVAILABLE          =0x00,
00405     LSM303C_ACC_YDA_AVAILABLE          =0x02,
00406 } LSM303C_ACC_YDA_t;
00407 
00408 #define     LSM303C_ACC_YDA_MASK      0x02
00409 status_t LSM303C_ACC_R_YDataAvail(void *handle, LSM303C_ACC_YDA_t *value);
00410 
00411 /*******************************************************************************
00412 * Register      : STATUS_REG2
00413 * Address       : 0X27
00414 * Bit Group Name: ZDA
00415 * Permission    : RO
00416 *******************************************************************************/
00417 typedef enum {
00418     LSM303C_ACC_ZDA_NOT_AVAILABLE          =0x00,
00419     LSM303C_ACC_ZDA_AVAILABLE          =0x04,
00420 } LSM303C_ACC_ZDA_t;
00421 
00422 #define     LSM303C_ACC_ZDA_MASK      0x04
00423 status_t LSM303C_ACC_R_ZDataAvail(void *handle, LSM303C_ACC_ZDA_t *value);
00424 
00425 /*******************************************************************************
00426 * Register      : STATUS_REG2
00427 * Address       : 0X27
00428 * Bit Group Name: ZYXDA
00429 * Permission    : RO
00430 *******************************************************************************/
00431 typedef enum {
00432     LSM303C_ACC_ZYXDA_NOT_AVAILABLE        =0x00,
00433     LSM303C_ACC_ZYXDA_AVAILABLE        =0x08,
00434 } LSM303C_ACC_ZYXDA_t;
00435 
00436 #define     LSM303C_ACC_ZYXDA_MASK    0x08
00437 status_t LSM303C_ACC_R_XYZDataAvail(void *handle, LSM303C_ACC_ZYXDA_t *value);
00438 
00439 /*******************************************************************************
00440 * Register      : STATUS_REG2
00441 * Address       : 0X27
00442 * Bit Group Name: XOR
00443 * Permission    : RO
00444 *******************************************************************************/
00445 typedef enum {
00446     LSM303C_ACC_XOR_NO_OVERRUN         =0x00,
00447     LSM303C_ACC_XOR_OVERRUN        =0x10,
00448 } LSM303C_ACC_XOR_t;
00449 
00450 #define     LSM303C_ACC_XOR_MASK      0x10
00451 status_t LSM303C_ACC_R_XDataOverrun(void *handle, LSM303C_ACC_XOR_t *value);
00452 
00453 /*******************************************************************************
00454 * Register      : STATUS_REG2
00455 * Address       : 0X27
00456 * Bit Group Name: YOR
00457 * Permission    : RO
00458 *******************************************************************************/
00459 typedef enum {
00460     LSM303C_ACC_YOR_NO_OVERRUN         =0x00,
00461     LSM303C_ACC_YOR_OVERRUN        =0x20,
00462 } LSM303C_ACC_YOR_t;
00463 
00464 #define     LSM303C_ACC_YOR_MASK      0x20
00465 status_t LSM303C_ACC_R_YDataOverrun(void *handle, LSM303C_ACC_YOR_t *value);
00466 
00467 /*******************************************************************************
00468 * Register      : STATUS_REG2
00469 * Address       : 0X27
00470 * Bit Group Name: ZOR
00471 * Permission    : RO
00472 *******************************************************************************/
00473 typedef enum {
00474     LSM303C_ACC_ZOR_NO_OVERRUN         =0x00,
00475     LSM303C_ACC_ZOR_OVERRUN        =0x40,
00476 } LSM303C_ACC_ZOR_t;
00477 
00478 #define     LSM303C_ACC_ZOR_MASK      0x40
00479 status_t LSM303C_ACC_R_ZDataOverrun(void *handle, LSM303C_ACC_ZOR_t *value);
00480 
00481 /*******************************************************************************
00482 * Register      : STATUS_REG2
00483 * Address       : 0X27
00484 * Bit Group Name: ZYXOR
00485 * Permission    : RO
00486 *******************************************************************************/
00487 typedef enum {
00488     LSM303C_ACC_ZYXOR_NO_OVERRUN       =0x00,
00489     LSM303C_ACC_ZYXOR_OVERRUN          =0x80,
00490 } LSM303C_ACC_ZYXOR_t;
00491 
00492 #define     LSM303C_ACC_ZYXOR_MASK    0x80
00493 status_t LSM303C_ACC_R_XYZDataOverrun(void *handle, LSM303C_ACC_ZYXOR_t *value);
00494 
00495 /*******************************************************************************
00496 * Register      : <REGISTER_L> - <REGISTER_H>
00497 * Output Type   : Acceleration
00498 * Permission    : RO 
00499 *******************************************************************************/
00500 status_t LSM303C_ACC_Get_Raw_Acceleration(void *handle, u8_t *buff); 
00501 status_t LSM303C_ACC_Get_Acceleration(void *handle, int *buff);
00502 
00503 #ifdef __cplusplus
00504 }
00505 #endif
00506 
00507 #endif